Method of inspecting planarity of wafer surface after etchback s

Details Method of inspecting planarity of wafer surface after etchback s Method of inspecting planarity of wafer surface after etchback s

1993-12-23

1995-05-30

Ruggiero, Joseph

Boots, shoes, and leggings

250234, 250306, 364490, 437 8, G06F 1546, H01J 314

Patent

active

054207967

ABSTRACT:
An integrated circuit (IC) fabrication process involves forming electronic devices on a semiconductor substrate. A metal layer is deposited thereover and then patterned to interconnect the semiconductor devices. A dielectric layer is deposited over the metal layer and substrate. The dielectric layer is etched back to prepare for the deposition of additional metal and dielectric layers. The etched surface is scanned by an atomic force microscope (AFM) to gather data representing the wafer surface roughness. The data is evaluated by a computer to generate at least one surface roughness signal. Depending on the value of the surface roughness signal, the IC fabrication process continues with the next step, a remedial action is taken, the IC fabrication process is adjusted for subsequent wafers, or the wafer is discarded.

REFERENCES:
patent: 4718019 (1988-01-01), Fillion et al.
patent: 5124927 (1992-06-01), Hopewell et al.
patent: 5254854 (1993-10-01), Betzig

Affiliated with

Also associated with

Rating

Method of inspecting planarity of wafer surface after etchback s does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of inspecting planarity of wafer surface after etchback s, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of inspecting planarity of wafer surface after etchback s will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-367541