Method of inspecting first layer overlay shift in global alignme

Details Method of inspecting first layer overlay shift in global alignme Method of inspecting first layer overlay shift in global alignme

1995-09-29

1996-08-13

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437229, 437924, H01L 2166

Patent

active

055455700

ABSTRACT:
An inspection pattern on a semiconductor wafer for inspecting is used to determine the degree of alignment of a first device layer during manufacture of integrated circuits on a semiconductor substrate the following steps. Form a zeroth layer on the substrate. The alignment marks and zeroth layer mother overlay inspection patterns are patterned simultaneously in the zeroth layer aligning to alignment marks formed in the zeroth layer. Then one forms a first layer on the substrate patterned simultaneously with formation of child overlay inspection patterns patterned in the same position as the zeroth layer mother inspection patterns to determine the overlay shift of the first layer.

REFERENCES:
patent: 4833621 (1989-05-01), Umatate
patent: 5332470 (1994-07-01), Crotti
patent: 5405810 (1995-04-01), Mizuno et al.
patent: 5407763 (1995-04-01), Pai

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