Method of inspecting a semiconductor wafer for defects

Details Method of inspecting a semiconductor wafer for defects Method of inspecting a semiconductor wafer for defects

1998-01-27

2002-06-11

Utech, Benjamin L. (Department: 1765)

Semiconductor device manufacturing: process

With measuring or testing

C438S016000, C438S692000, C438S693000, C438S706000, C438S745000, C438S959000

Reexamination Certificate

active

06403385

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an integrated circuit or semiconductor device. More particularly, the present invention relates to a method for decorating a semiconductor wafer to reveal defects.
BACKGROUND OF THE INVENTION
In the fabrication of integrated circuits (ICs), chemical mechanical planarization (CMP) is widely used for polishing inter-level dielectrics (ILD) on multi-layer devices which utilize interconnect structures. More recently, isolation schemes like shallow trench isolation (STI) have also made use of CMP.
In general, a CMP process involves holding a semiconductor wafer against a rotating polishing pad. A polishing slurry is added, e.g. a solution of alumina or silica, as the abrasive medium. The polishing slurry contains small, abrasive particles that polish the surface of the wafer. The content of this slurry determines its operability. Throughout the process, the wafer is kept under controlled chemical, pressure, velocity and temperature conditions.
CMP tends to leave surface defects, such as microscratches and particulate defects, on the surface or layer being planarized or polished. A microscratch is a small scratch, typically about 5 micrometers to 20 micrometers in length and 500 Å to 1000 Å in depth. These defects can result in connectivity problems between layers and components of the semiconductor device. Connectivity problems are compounded by subsequent mask and etch processes, the expected results of which can be disturbed by the presence of such defects, ultimately adversely effecting product yield and production cost.
Surface defects, such as microscratches, can be reduced or eliminated by adjusting the content and filtration of the slurry, and adjusting the composition of the layer being polished, e.g. an oxide layer, for greater resiliency to defects. However, microscratches are difficult to detect. Thus, in a fabrication process comprising multiple steps of etching, masking and deposition of layers on a substrate, it is difficult to identify which of these steps is causing the defects.
A variety of techniques currently exist for inspecting the surface of semiconductor wafers. These techniques include light scattering topography (LST), stylus profilometry, phase shift interferometry, and atomic force microscopy (FM). However, surface defects are not always readily visible with these conventional inspection methods due to the small size of microscratches and because they are typically filled with unwanted residual from a previously deposited layer. Thus, heretofore it has not been possible to identify microscratches in a post-CMP substrate and, consequently, it has not been possible to identify and optimize the step causing the microscratches.
Thus, there is a need for a semiconductor wafer inspection process that reveals surface defects, such as microscratches, to aid in isolation and optimization of defect-causing steps in the semiconductor fabrication process.
SUMMARY OF THE INVENTION
The present invention relates to a method of inspecting a semiconductor wafer for defects by providing a layer of material on the wafer, polishing the wafer to remove a portion of the layer, dipping the wafer in an etchant for a period of time, and inspecting the wafer for defects. The step of dipping reveals defects in the wafer that were previously undetectable, allowing isolation and optimization of the fabrication step causing the defects.
The present invention further relates to a method of inspecting a semiconductor wafer for defects due to chemical mechanical planarization (CMP) by providing an oxide layer on the wafer, polishing the wafer to remove a portion of the oxide layer, etching the wafer in a dilute etchant solution for a period of time, and inspecting the wafer for defects so that defects due to the CMP step can be examined.
The present invention further relates to a method of inspecting a semiconductor wafer for defects due to chemical mechanical planarization by providing a semiconductor wafer, providing an oxide layer on the wafer, polishing the wafer by CMP to remove at least a portion of the oxide layer, decorating the wafer with an etchant, and inspecting the wafer for defects using an optical inspection tool to determine a defect count.


REFERENCES:
patent: 3979238 (1976-09-01), Justice
patent: 4238275 (1980-12-01), Shih
patent: 4316765 (1982-02-01), Thiel
patent: 5378318 (1995-01-01), Weiling et al.
patent: 5510652 (1996-04-01), Burke et al.
patent: 5514245 (1996-05-01), Doan et al.
patent: 5535005 (1996-07-01), Mukherjee-Roy et al.
patent: 5575886 (1996-11-01), Murase
patent: 5650619 (1997-07-01), Hudson
patent: 5663797 (1997-09-01), Sandhu
Ben-Porath et al., Automatic defect classification with invariant core classes, WO 00/03234, Jan. 20, 2000, pp. 1-53.*
Scratch Measurement Technique, IBM Technical Disclosure Bulletin, vol. 34, No. 4B, 263 anf 264, Sep. 1991.

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