Method of inhibiting degradation of ultra short channel charge-c

Details Method of inhibiting degradation of ultra short channel charge-c Method of inhibiting degradation of ultra short channel charge-c

1995-06-07

1997-07-22

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

36518527, 36518531, G11C 1604

Patent

active

056509642

ABSTRACT:
A process for discharging a floating gate semiconductor device formed in a semiconductor substrate, the device having a first active region, a second active region, a charge holding region, and a channel between the first and second active regions, the channel having a length defined by a distance below the charge holding region between the first and second active regions. The process comprises the steps of: applying a first positive voltage of about 4-8 volts to the first active region; applying a second voltage in the range of about 0.5-3 volts to the second active region; applying a third voltage in the range of minus 8 volts to the charge holding region; and coupling the substrate to ground. The first active region may comprise either a source or a drain region of a MOSFET, and the second active region may comprise a source region or a drain region of a MOSFET. In a further aspect an array of floating gate transistors, each transistor comprising a source, drain, gate and floating gate, each floating gate including an electric charge; and control logic coupled to the transistors, for selectively addressing the transistors is disclosed. In the apparatus, to discharge the floating gates of each transistor in the array: each source is coupled in common to a first voltage; each drain is coupled in common to a second voltage lower than the first voltage; the substrate is coupled to ground; and each floating gate is coupled to a negative voltage.

REFERENCES:
patent: 4884239 (1989-11-01), Ono
patent: 5077691 (1991-12-01), Haddad
patent: 5396459 (1995-03-01), Arakawa
patent: 5414669 (1995-05-01), Tedrow
patent: 5416738 (1995-05-01), Shrivastava
patent: 5452248 (1995-09-01), Naruke
Jian Chen, et al., Subbreakdown Drain Leakage Current in MOSFET, IEEE Electron Device Lett., vol. EDL-8, No. 11, pp. 515-517, Nov. 1987.
T.Y. Chan, et al., The Impact of Gate-Induced Drain Leakage Current on MOSFET Scaling, IEDM Technical Digest, pp. 718-721, 1987.
Chi Chang, et al., Corner-Field Induced Drain Leakage In Thin Oxide MOSFETS, IEDM Technical Digest, pp. 714-717, 1987.

Affiliated with

Also associated with

Rating

Method of inhibiting degradation of ultra short channel charge-c does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of inhibiting degradation of ultra short channel charge-c, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of inhibiting degradation of ultra short channel charge-c will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1564398