Method of incremental statistical static timing analysis...

Details Method of incremental statistical static timing analysis... Method of incremental statistical static timing analysis...

2009-05-31

2011-10-25

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Logic design processing

C716S110000, C716S111000, C716S112000, C716S113000, C716S134000, C703S019000

Reexamination Certificate

active

08046725

ABSTRACT:
Provided is a method of incremental SSTA (statistical static timing analysis) of a digital circuit, the method including a first step in which, when a gate is replaced in the digital circuit, delay propagation is performed from a node of a replaced gate to a virtual sink node based on SSTA; a second step in which, if a changed value of a gate timing yield at each gate which propagates delay toward the virtual sink node is smaller than a predetermined threshold value, delay propagation with respect to a fanout gate of the corresponding gate is stopped; and a third step in which, when a delay with respect to the node of the replaced gate is propagated to the virtual sink node, a new timing yield is calculated at the virtual sink node.

REFERENCES:
patent: 7000205 (2006-02-01), Devgan et al.
patent: 7861199 (2010-12-01), Visweswariah et al.
patent: 2005/0066296 (2005-03-01), Visweswariah
patent: 2008/0307379 (2008-12-01), Visweswariah
patent: 2009/0013294 (2009-01-01), Visweswariah
Jin Wook Kim, Wook Kim, Hyoun Soo Park and Young Hwan Kim, Incremental Statistical Static Timing Analysis with Gate Timing Yield Emphasis, IEEE, Dec. 2008, pp. 1016-1019.
C. Visweswariah et al., “First-order incremental block-based statistical timing analysis,”IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, No. 10, pp. 2170-2180, Oct. 2006.

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