Method of increasing the surface area of a mini-stacked capacito

Details Method of increasing the surface area of a mini-stacked capacito Method of increasing the surface area of a mini-stacked capacito

1992-02-07

1992-09-08

Thomas, Tom

Fishing, trapping, and vermin destroying

437 47, 437 48, 437 60, 437228, 437235, 437919, H01L 2170

Patent

active

051458012

ABSTRACT:
A mini-stack capacitor process, developed for DRAM fabrication, is used to create a stacked capacitor by depositing multiple layers of dielectric over existing digit and word lines. The exposed top dielectric is then masked and etched away between two adjacent digit lines, the resist is stripped and subsequent etches (or etch) remove(s) the remaining dielectric layers thereby exposing the underlying conductively doped diffusion region. The storage node poly is then deposited and patterned, followed by subsequent depositions of a cell dielectric and cell plate poly. The selection of the number of dielectrics used and the type and/or sequence of dielectric etches used are the crux of the invention that substantially increases the surface area of a given stacked capacitor by approximately 40 to 80%.

REFERENCES:
patent: 4342617 (1982-08-01), Fu et al.
patent: 4970564 (1990-11-01), Kimura et al.
patent: 5043298 (1991-08-01), Yamada et al.
"3-Dimensional Stacked Capacitor Cell for 16M And 64M Drams", by T. Ema et al., pp. 592-595, IEDM 88.

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