Method of increasing the layout efficiency of dies on a wafer an

Details Method of increasing the layout efficiency of dies on a wafer an Method of increasing the layout efficiency of dies on a wafer an

1992-07-17

1994-08-23

Thomas, Tom

Fishing, trapping, and vermin destroying

437 51, 148DIG28, H01L 21304

Patent

active

053407725

ABSTRACT:
Certain non-square dies, such as triangular dies, greatly elongated rectangular dies, parallelogram dies, trapezoidal, and the like, are able to be laid out in the area of a circular semiconductor wafer more "efficiently" than square dies. Further, a peripheral area of these certain non-square dies is advantageously increased relative to the area contained within the peripheral area, to accommodate increased I/O connections to the active elements of the die.

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