Method of increasing the layout efficiency of dies on a wafer, a

Details Method of increasing the layout efficiency of dies on a wafer, a Method of increasing the layout efficiency of dies on a wafer, a

1992-11-18

1994-08-23

Hille, Rolf

Active solid-state devices (e.g., transistors, solid-state diode

Physical configuration of semiconductor

With peripheral feature due to separation of smaller...

257618, 437226, H01L 2102, H01L 21302

Patent

active

053410246

ABSTRACT:
Certain non-square dies, such as triangular dies, greatly elongated rectangular dies, parallelogram dies, trapezoidal, and the like, are able to be laid out in the area of a circular semiconductor wafer more "efficiently" than square dies. Further, a peripheral area of these certain non-square dies is advantageously increased relative to the area contained within the peripheral area, to accommodate increased I/O connections to the active elements of the die.

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"Volume Production Of Unique Plastic Surface-Mount Modules For The IBM 80-ns 1-Mbit Dram Chip By Area Wire Bond Techniques", by Ward, IEEE, 1988, pp. 552-557.

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