Method of improving the planarization of wiring by CMP

Details Method of improving the planarization of wiring by CMP Method of improving the planarization of wiring by CMP

1999-11-08

2002-10-15

Nguyen, Ha Tran (Department: 2812)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S633000, C438S637000, C438S660000, C438S645000, C438S678000, C438S687000

Reexamination Certificate

active

06465354

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a manufacturing method of semiconductor device provided with a plurality of embedded wiring and/or through holes.
DESCRIPTION OF THE PRIOR ART
A formation method of conventional embedded wiring is explained referring to
FIGS. 1A
to
1
D.
Firstly, as shown in
FIG. 1A
, silicone nitride film
2
(film thickness 100 nm) and silicone oxide film
3
(film thickness 1000 nm) are formed on silicone substrate
1
in order. Next, a plurality of holes which come to the silicone nitride film
2
are formed within the silicone oxide film
3
using dry etching.
Next, as shown in
FIG. 1B
, the manufacturing process deposits barrier metal layer
4
consisting of titanium ‘Ti’ and titanium nitride ‘TiN’ all over the surface thereof by sputtering method. Film-thickness thereof is 200 Å. Continuously, the manufacturing process deposits seed metal layer consisting of copper thereon by sputtering method for growing copper plating (not illustrated). Further, uninterruptedly, the manufacturing process immerses the silicone substrate
1
into copper sulfate aqueous solution with solution temperature about 25° C., to form metal plating layer
5
consisting of copper by electrolytic plating method. A power-supply for forming the plating, for instance, uses direct current power-supply, setting with current value as 0.5 A/dm
2
. Here, layer thickness of metal plating layer
5
is set to approximately 900 nm in flat part. Status thereof is indicated in FIG.
1
B.
The manufacturing process implements annealing about the substrate subjected to plating as mentioned above, in such a way as degree of 30 minutes with 300° C. Due to this annealing, grain-size grows larger and resistance value is lowered.
Subsequently, the manufacturing process polishes the metal plating layer
5
by ‘CMP’ (Chemical Mechanical Polishing) to make surface of the substrate flat, thus causing embedded wiring is perfected (
FIGS. 1C
,
1
D).
However, above-described prior art involves following problems:
In manufacturing process of ‘CMP’ shown in
FIGS. 1C
,
1
D, it is necessary to take a large amount of time for polishing such that the metal plating layer
5
on the silicone oxide layer
3
does not rest. Here, polishing speed in relation to the metal plating layer
5
is large in comparison with polishing speed in relation to the barrier metal layer
4
or the silicone oxide layer
3
. For that reason, in the manufacturing process of ‘CMP’ after exposure of the barrier metal layer
4
, wiring dense part in which a lot of embedded parts of the metal plating layer
5
exist is added high pressure on the barrier metal layer
4
and/or the silicone oxide layer
3
in comparison with wiring isolated part in which embedded part of the metal plating film exists not so many. For that reason, ‘CMP’ is progressed in excess at the wiring dense part, thus problem occurs that surface of insulation layer
3
becomes trench as shown in FIG.
1
D. This phenomenon is ‘Erosion’.
FIG. 2
shows the above-described phenomenon on graph. In
FIG. 2
, the horizontal axis represents polishing time, and the vertical axis represents distance (height) from a back surface of the substrate to a surface of the substrate. The surface of the substrate before starting of polishing is approximately flat, and grain-size of plating metal layer
5
placed at the upper part than the barrier metal layer
4
is approximately uniform in any place. For that reason, in the initial stage of start of polishing, polishing of the wiring isolated part and polishing of wiring dense part are progressed with equal speed. Next, when the whole metal plating layer is removed, before the barrier metal layer
4
is exposed (T
1
in FIG.
2
), after that, polishing becomes polishing of the barrier metal layer
4
and the silicone oxide layer
3
, therefore, the polishing speed becomes slow suddenly. On the contrary, in the wiring dense part, since a lot of embedded parts of the metal plating layer
5
exist, polishing speed after ‘T
1
’ becomes larger than that of the wiring isolated part according to the reason described above. For that reason, ‘Erosion’ occurs.
As described above, when ‘Erosion’ occurs, flatness of substrate surface deteriorates. The deterioration of the flatness becomes more conspicuous in the case of multi-layer structure, thus it causes problem that short circuit of wiring part and so forth occur. Further, when it forms embedded wiring, section area becomes small, problem occurs that wiring resistance becomes large.
SUMMARY OF THE INVENTION
In view of the foregoing, it is an object of the present invention, in order to overcome the above-mentioned problems to provide manufacturing method of a semiconductor device including wiring dense part (dense pattern) and wiring isolated part, which manufacturing method enables occurrence of an ‘Erosion’ to be prevented.
It is another object of the present invention to provide manufacturing method of a semiconductor device including wiring dense part (dense pattern) and wiring isolated part, which manufacturing method enables occurrence of a micro-scratch to be prevented.
According to a first aspect of the present invention, in order to achieve the above mentioned object, there is provided a manufacturing method of a semiconductor device which comprises the steps of a first manufacturing step in which it forms insulation layer on a semiconductor substrate, and it forms a plurality of trench-parts at prescribed points on the insulation layer, before it forms metal plating layer on the whole surface so as to embed the plurality of trench-parts, a second manufacturing step for implementing annealing so as to cause grain-size of metal plating layer in a dense pattern where the trench-part is formed densely to be smaller than grain-size of metal plating layer in a pattern except for the dense pattern, and a third manufacturing step for causing surface of substrate to be flat while polishing the metal plating layer and the insulation layer.
In general, metal material which is subjected to plating has structure which small size grain is gathered to be formed. When the metal plating layer undergoes annealing, grain-size of the grain increases while facing in the constant direction. Thus resistance value of plating layer decreases due to the fact that the grain-size increases, with the result that characteristic as conductive film is stabilized preferably.
The conventional annealing process after plating, for instance, in the case of copper plating, the annealing has been implemented in high temperature of more than 300° C. for enhancing productivity. Under such the condition, grain is growing with uniform speed all over the surface in spite of shape of pattern for forming plating layer. Consequently, in the conventional process, there does not occur difference in grain-size between dense pattern of trench-part and another pattern except for dense-pattern. To the contrary, in the present invention, a second manufacturing step implements annealing in such a way that the grain-size of the metal plating layer in the dense pattern in which the trench-part is formed densely becomes smaller than the grain-size of the metal plating layer in the pattern except for the dense pattern.
According to an investigation of the present invention, when it causes the grain-size of metal plating layer to be small, it is capable of suppressing speed of polishing by ‘CMP’ and so forth effectively. For that reason, polishing of the plating layer in the dense pattern is suppressed by implementing annealing according to the above-described method, thus occurrence of ‘Erosion’ can be prevented.
According to a second aspect of the present invention, there is provided a manufacturing method of semiconductor device which comprises the steps of a first manufacturing step in which it forms insulation layer on a semiconductor substrate, and it forms a plurality of trench-parts at prescribed points on the insulation layer, before it forms metal plating layer on the whole surface so as to embed the

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