Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
2001-12-20
2004-06-01
Tsai, H. Jey (Department: 2812)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S238000, C438S255000, C438S627000
Reexamination Certificate
active
06743641
ABSTRACT:
FIELD OF INVENTION
The present invention relates to a magnetic random access memory (MRAM) and a fabricating method thereof, and more particularly to a method of improving surface planarity prior to bit material deposition.
BACKGROUND OF THE INVENTION
Magnetic random access memories (MRAMs) employ magnetic multilayer films as storage elements. When in use, an MRAM cell stores information as digital bits, which in turn depend on the alternative states of magnetization of thin magnetic multilayer films forming each memory cell. As such, the MRAM cell has two stable magnetic configurations, high resistance representing a logic state
0
and low resistance representing a logic state
1
, or vice versa.
A typical multilayer-film MRAM includes a number of bit or digit lines intersected by a number of word lines. At each intersection, a film of a magnetically coercive material is interposed between the corresponding bit line and word line. Thus, this magnetic material and the multilayer films from the digit lines form a magnetic memory cell which stores a bit of information.
The basic memory element of an MRAM is a patterned structure of a multilayer material, which is typically composed of a stack of different materials, such as copper (Cu), tantalum (Ta), permalloy (NiFe) or aluminum oxide (Al
2
O
3
), among others. The stack may contain as many as ten different overlapping material layers and the layer sequence may repeat up to ten times. Fabrication of such stacks requires deposition of the thin materials layer by layer, according to a predefined order.
FIG. 1
shows an exemplary conventional MRAM structure including MRAM stacks
22
which have three respective associated bit or digit lines
18
. The digit lines
18
, typically formed of copper (Cu), are first formed in an insulating layer
16
formed over underlayers
14
of an integrated circuit (IC) substrate
10
. Underlayers
14
may include, for example, portions of integrated circuitry, such as CMOS circuitry. A pinned layer
20
, typically formed of ferromagnetic materials, is provided over each digit line
18
. A pinned layer is called “pinned” because its magnetization direction does not change during operation of the memory device. A sense layer
21
is provided over each associated pinned layer
20
. The MRAM stacks
22
are coupled to a word line
23
that intersects three pinned layers
20
and associated sense layers
21
. The word line
23
and bit line
18
may also be interchanged.
An MRAM device integrates magnetic memory elements and other circuits, for example, a control circuit for magnetic memory elements, comparators for detecting states in a magnetic memory element, input/output circuits, etc. These circuits are fabricated in the process of CMOS technology in order to lower the power consumption of the MRAM device. The CMOS process requires high temperature steps which exceeds 300° C. for depositing dielectric and metal layers and annealing implants, for example.
In addition, a magnetic memory element includes very thin layers, some of them are tens of angstroms thick. The performance of the magnetic memory element is sensitive to the surface conditions on which magnetic layers are deposited. Accordingly, it is necessary to form a flat surface at certain stages of fabrication to prevent the characteristics of an MRAM device from degrading. The present invention provides a method of fabricating an MRAM having a more planar surface prior to deposition of the magnetic stack.
SUMMARY OF THE INVENTION
The present invention provides a method of improving surface planarity prior to bit material deposition in MRAM structures. In an exemplary embodiment of the invention, a first conductor in a trench is provided in an insulating layer and an upper surface of the insulating layer and the first conductor is planarized. This leaves a roughened upper surface on the conductor. Further, a material layer is formed over the planarized upper surface of the insulating layer and the first conductor and an upper portion of the material layer is again planarized or flattened while leaving intact a lower portion of the material layer over the insulating layer and the first conductor.
REFERENCES:
patent: 5354712 (1994-10-01), Ho et al.
patent: 6110648 (2000-08-01), Jang
patent: 6174737 (2001-01-01), Durlam et al.
patent: 6181013 (2001-01-01), Liu et al.
patent: 6326218 (2001-12-01), Yunogami et al.
patent: 2002/0098705 (2002-07-01), Low
Written Opinion, PCT/US 02/40352.
Drewes Joel A.
Yates Donald L.
Dickstein , Shapiro, Morin & Oshinsky, LLP
Tsai H. Jey
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