Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2002-05-17
2004-08-17
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S435000
Reexamination Certificate
active
06777308
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method for improving dielectric deposition and trench fill in semiconductor substrates or layers utilizing high-density plasma chemical vapor deposition (HDP-CVD). More particularly, the present invention is directed toward a method and system for improving the trench fill in shallow trench isolation (STI) structures.
Electronic devices such as field-effect transistors (FETs) are useful in fabricating integrated circuits such as those used in memory chips and microprocessors. The FETs used in high performance complementary metal oxide semiconductor (CMOS) circuits require advanced isolation techniques for filling recessed field oxide regions. One common isolation technique is known as local oxidation of silicon (LOCOS).
In LOCOS, a silicon nitride layer is deposited and patterned to leave islands of silicon nitride over on a semiconductor wafer. Silicon oxide is then grown on the areas of exposed silicon, and the silicon nitride is removed. This leaves wafer surface regions ready for device formation and separated by isolating regions of oxide. However, the use of LOCOS may cause isolation problems such as the formation of a bird's beak spur that grows under the edge of the blocking silicon nitride layer. This bird's beak takes up surface area, which is undesirable as circuit areas decrease. Additionally, the bird's beak induces stress damage in the silicon during the oxidation step from the mismatch in thermal expansion properties between silicon nitride and silicon.
An alternative to LOCOS is shallow trench isolation (STI). STI can solve the bird's beak problem. STI regions are used to isolate structures in semiconductor devices. The STI process begins with the formation of islands of nitride. A trench etch is then performed to trench the silicon around the islands of nitride. The trenches are filled with a dielectric such as an oxide to provide isolation regions. STI regions consume less silicon than other isolation methods. Thus, STI allows for smaller device geometry, and STI is generally used for sub 250 nm devices. Void free trench fill of oxides in STI trenches is extremely important for providing isolation. However, void free trench fill is difficult to achieve in STI trenches.
Chemical vapor deposition (CVD) has been used extensively to deposit dielectric material in trenches. During deposition, dielectric material will collect on the corners of the trenches, and overhangs will form at the corners. These overhangs typically grow together faster than the trench is filled, and a void in the dielectric material filling the gap is created. Many techniques have been utilized in attempts to solve the trench fill problem.
One technique which attempts to solve this problem is deposition and simultaneous etch back of the dielectric layer. This technique may be accomplished using HDP-CVD. Typically, HDP-CVD is carried out in a process chamber, such as an Ultima HDP-CVD® chamber, commercially available from Applied Materials (see U.S. Pat. No. 6,182,602 to Redecker et al.). Precursor gases such as silane and oxygen are flowed into the chamber along with an inert gas that is typically argon. A plasma is formed in a reaction zone proximate to the surface of the substrate by the application of radio frequency (RF) energy. The deposition gases disassociate and react to form a silicon dioxide layer. The relatively non-reactant inert gas is ionized and used to etch the silicon dioxide layer during deposition to keep the gaps open. The flow rates, RF power and other parameters are typically controlled to produce the desired rate of deposition and etch. In this manner, trenches in a semiconductor substrate may be successfully filled. However, such techniques do not always produce a void free trench fill. Additionally, HDP-CVD processes can cause particles to be deposited in the silicon dioxide layer. Particles may be deposited in the silicon dioxide layer from contaminants on the process chamber walls or from species that are formed in the plasma itself. Such particles are undesirable because they mar the smooth surface of the silicon dioxide layer and can compromise the insulating properties of the silicon dioxide.
Therefore, there is a need for a method of HDP-CVD that can produce a void free trench fill for trenches of varying depth and width in semiconductor substrates and layers. Additionally, there is a need for a method of HDP-CVD that balances the number of particles in the silicon dioxide layer with the need for void free gap fill. Finally, there is need for a method of HDP-CVD that can be successfully integrated with STI processes.
SUMMARY
This need is met by the present invention that provides a method for depositing trench-filling material and isolation structures having substantially void free trench fill. This method may be used in conjunction with conventional processing to provide structures requiring trench fill with a dielectric. The method is especially useful for shallow trench isolation structures.
In accordance with one embodiment, a method for filling a trench in a layer disposed in a process chamber is provided. The method comprises: providing a semiconductor layer having at least one trench therein; flowing a first precursor gas and a first inert gas into said process chamber and forming a first plasma therein; depositing a first layer of trench-filling material from said first plasma into said at least one trench; flowing a second precursor gas and second inert gas into said process chamber and forming a second plasma therein; and depositing a second layer of trench-filling material from said second plasma to substantially fill said at least one trench. The first inert gas is selected from the group consisting of helium, neon, argon, and krypton and combinations thereof, and the second inert gas is selected from the group consisting of helium, neon, argon, and krypton and combinations thereof. The first and second inert gases are typically selected to be different inert gases. The first inert gas is generally selected from the group consisting of helium and neon and combinations thereof, and the second inert gas is generally selected from the group consisting of argon and krypton and combinations thereof. The first precursor gas generally comprises a silicon precursor and an oxygen precursor, and the second precursor gas generally comprises a silicon precursor and an oxygen precursor. The trench filling material generally comprises silicon dioxide. The layer generally comprises a semiconductor substrate, or the layer may comprise silicon.
The process chamber may be purged of the first inert gas after the deposition of the first layer. The purging may be accomplished by terminating the first plasma after the deposition of the first layer. Alternatively, the purging may be accomplished by forming an oxygen plasma in the deposition chamber after the deposition of the first layer. In yet another embodiment, the purging may be accomplished by venting the first inert gas out of the process chamber after the deposition of the first layer.
Silane and molecular oxygen may comprise the first precursor gases. The silane may be flowed into the process chamber at a flow rate of about 1-150 sccm. Molecular oxygen may be flowed into the process chamber at a flow rate of about 10-300 sccm, and the first inert gas maybe flowed into the chamber at a flow rate of about 1-2000 sccm. Typically, the first inert gas will be flowed into the chamber at a flow rate of about 200 sccm. Silane and molecular oxygen may comprise the second precursor gases. Silane may be flowed into the process chamber at a flow rate of about 1-150 sccm, and oxygen may be flowed into the process chamber at a flow rate of about 10-300 sccm. The second inert gas may be flowed into the chamber at a flow rate of about 1-2000 sccm. Typically, the second inert gas will be flowed into the chamber at a flow rate of about 200 sccm.
In an alternative embodiment, a method for a filling a trench in a layer comprises providing a semicondu
Li Li
Li Weimin
Sandhu Gurtej S.
Dinsmore & Shohl LLP
Pham Long
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