Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Treating process fluid by means other than agitation or...
Reexamination Certificate
1999-09-01
2001-12-18
Gorgos, Kathryn (Department: 1741)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Treating process fluid by means other than agitation or...
C205S123000
Reexamination Certificate
active
06331237
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to plating metals in semiconductor chip applications. In particular, the present invention relates to protecting very thin current carrying layers from attack by a plating solution.
BACKGROUND OF THE INVENTION
Metals are utilized for a variety of applications in semiconductor chips. One example of such applications includes the interconnect wiring. One means of depositing interconnect structures of some metals is electroplating on to semiconductor structures.
Recently, copper has started to replace aluminum in interconnect structures in integrated circuit chips. Replacement of aluminum with copper stems at least in part from the lower electrical resistivity of copper. As a result, utilizing copper has resulted in an improvement in IC chip performance. These advantages are described by Luther et al., Proceedings of the 10th International IEEE VLSI Multilevel Interconnection Conference, 1993, p. 15; and by Edelstein, Proceedings of the 12th International IEEE VLSI Multilevel Interconnection Conference, 1995, p. 301, the entire contents of both of which are hereby incorporated by reference.
One method that may be utilized to deposit copper for on-chip interconnect structures is the damascene method. U.S. Pat. No. 5,612,254, the entire contents of the disclosure of which are incorporated herein by reference, discloses a damascene process. Typically, copper is electroplated to form the structures, as described by Andricacos et al., IBM J. Res. Develop., 42, 567 (1998), the entire contents of the disclosure of which is hereby incorporated by reference. Electroplating and the damascene method provide a lower cost versatile method for deposition of copper.
Electroplated damascene technology typically starts with the deposition on a semiconductor wafer and patterning of dielectric material. Next, a barrier material may be deposited over an entire surface of the wafer including the dielectric material and any underlying portions of the semiconductor wafer exposed by the patterning. The barrier material may serve to isolate the silicon circuitry formed in and on the semiconductor wafer from the copper interconnection.
Subsequent to providing the layer of barrier material, a thin conducting layer may be deposited over the barrier material. This “seed” layer may act to carry the electrical current for the electroplating process. While the thin conducting layer may comprise any metal(s) or alloy(s), typically, the thin conducting layer is copper.
After providing a seed layer, the metal to make up the interconnection structure may be electrodeposited over the entire surface of the wafer, filling the patterns of lines and vias in the dielectric and simultaneously forming an “overburden” on the top of the dielectric. The overburden may then be removed. Typically, the removal is accomplished by chemical-mechanical polishing.
In some cases, a dual damascene technique may be utilized. A dual damascene technique is described by U.S. Pat. No. 5,814,557, the entire contents of the disclosure of which is hereby incorporated by reference. According to the dual damascene technique, two levels, a via level and a line level, may be patterned and deposited in a single step. By creating both of these levels simultaneously, a dual damascene technique may provide cost savings.
SUMMARY OF THE INVENTION
The present invention provides a method of reducing etching of a seed layer by a plating solution prior to the initiation of plating. The method includes diminishing the etching power of the plating solution.
Additionally, the present invention concerns a method of electroplating interconnection structures on a semiconductor wafer. The method includes depositing a layer of dielectric material on a surface of a semiconductor wafer comprising integrated circuits. The layer of dielectric material is patterned, exposing a portion of the semiconductor wafer. The patterning matches a desired pattern of interconnect structures to be deposited on the semiconductor wafer. A layer of a barrier material is deposited over the patterned layer of dielectric material. An electrically conducting seed layer is deposited on the layer of barrier material. The wafer is introduced into a plating solution having a lowered etch rate with respect to the metal included in the conducting seed layer. A plating current is initiated to electrodeposit at least one metal over the entire surface of the wafer. An overburden of electroplated metal and the seed layer and barrier layer lying on top of the layer of dielectric material are removed leaving a planar structure of interconnect lines and/or vias isolated by the dielectric material.
Furthermore, the present invention pertains to a deaerated plating solution. The solution includes at least one metal to be plated on a seed layer, at least one acid, and a level of dissolved oxygen less than about 10
−7
to about 5×10
−6
moles/liter.
Still further, the present invention provides a plating tool that includes a plating cell and a plating solution reservoir. A supply line feeds plating solution from the plating solution reservoir to the plating cell. A return line feeds plating solution from the plating cell to the plating solution reservoir. An inert gas supply introduces inert gas into the plating solution.
Still other objects and advantages of the present invention will become readily apparent by those skilled in the art from the following detailed description, wherein it is shown and described only the preferred embodiments of the invention, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive.
REFERENCES:
patent: 5198273 (1993-03-01), Ando et al.
patent: 5425859 (1995-06-01), Tench et al.
patent: 5612254 (1997-03-01), Mu et al.
patent: 5814557 (1998-09-01), Venkatraman et al.
patent: 5968333 (1999-10-01), Nogami et al.
patent: 5972192 (1999-10-01), Dubin et al.
patent: 6146517 (2000-11-01), Hoinkis
D. C. Edelstein, “Advantages of Copper Interconnects,” 1995 VMIC Conference, Jun. 27-29, 1995, 1995 ISMIC vol. 104, pp. 301-307.
Luther, B., et al., “Planar Copper-Polyimide Back End Use of the Line Interconnections for ULSI Devices,” 1993 VMIC Conference, Jun. 8-9, 1995, 1993 ISMIC vol. 102, pp. 15-21.
Andricacos, P.C., et al., “Damascene Copper Electroplating for Chip Interconnections,”J. Res. Develop., vol. 42, No. 5, Sep. 1998, pp. 567-574.
Andricacos Panayotis C.
Horkans W. Jean
Kwietniak Keith T.
Locke Peter S.
Uzoh Cyprian E.
Connolly Bove & Lodge & Hutz LLP
Gorgos Kathryn
International Business Machines - Corporation
Smith-Hicks Erica
Trepp, Esq Robert M.
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