Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having substrate registration feature
Reexamination Certificate
2004-03-30
2004-11-16
Tsai, H. Jey (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having substrate registration feature
C438S238000, C438S381000
Reexamination Certificate
active
06818524
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor processes. More particularly, the present invention relates to a semiconductor process that is capable of improving alignment accuracy and preventing M
0
metal open problem in the alignment mark region.
2. Description of the Prior Art
A DRAM chip is an integrated circuit (IC) made of millions of transistors and capacitors. Typically, a transistor and a capacitor are paired to create a DRAM cell, which represents a single bit of data. The capacitor holds the bit of information—a “0” or a “1”. The transistor acts as a switch that lets the control circuitry on the memory chip read the capacitor or change its state. As known in the art, memory cells are etched onto a silicon wafer in an array of columns (bitlines) and rows (wordlines). The intersection of a bitline and wordline constitutes the address of the memory cell.
Briefly, after the formation of the wordlines, a dielectric layer is deposited on the wordlines and in inter-space between these wordlines. Contact holes are etched into the dielectric layer. Metals such as tungsten are deposited inside the contact holes, followed by chemical mechanical polishing (CMP).
FIG. 1
to
FIG. 4
illustrate the formation of bitline contact devices in the fabrication of a DRAM chip according to the prior art method. As shown in
FIG. 1
, a semiconductor substrate
10
for making a DRAM device is provided having thereon a memory array area
11
and a peripheral area
21
. A plurality of wordlines
12
,
14
, and
16
are defined on the main surface of the semiconductor substrate
10
. Alignment mark (AM)
30
, which is used to align a photo mask having a contact-hole pattern thereon with the wafer that is mounted on a stepper and scanner, is located in the peripheral area
21
of the semiconductor substrate
10
. On the surface of the semiconductor substrate
10
, a borophosposilicate glass (BPSG) layer
22
and a TEOS oxide layer
24
are deposited. A polysilicon layer
26
is deposited on the TEOS oxide layer
24
. The polysilicon layer
26
acts as a hard mask in subsequent contact hole etching process.
As shown in
FIG. 2
, before performing the lithographic process and etching of the bitline contact holes (CB), an alignment window
29
that exposes a portion of the TEOS oxide layer
24
is formed in the polysilicon layer
26
. The alignment window
29
is directly located above the alignment mark
30
, such that the stepper and scanner may use the alignment mark
30
to align the photo mask with the wafer. To form the alignment window
29
, a GV photo resist
28
is formed on the polysilicon layer
26
having an opening located directly above the alignment mark
30
. The exposed polysilicon layer
26
is then etched away through the opening. The GC photo resist
28
is removed.
As shown in
FIG. 3
, after forming the alignment window
29
, a CB photo resist
32
is formed on the polysilicon layer
26
. Through the alignment window
29
and the alignment mark
30
, a mask-wafer alignment is then carried to ensure precise image transfer. Thereafter, by means of exposure and development, a contact hole opening or CB opening
40
is created in the CB photo resist
32
.
As shown in
FIG. 4
, using both the CB photo resist
32
and the polysilicon layer
26
as an etching hard mask, a dry etching process is carried out to etching the bitline contact hole (CB) into the polysilicon layer
26
, the TEOS oxide layer
24
, and the BPSG layer
22
through the CB opening
40
, thereby forming a contact hole
50
between two wordlines
12
and
14
. It is noteworthy that this dry etching process simultaneously etches away the TEOS oxide layer
34
and BPSG layer
22
through the alignment window to produce a recess
52
in the peripheral area
21
. The subsequent zeroth level (M
0
) metallization processes following the formation of contact hole
50
are known in the art. Metal such as tungsten, titanium, or titanium nitride is deposited on the substrate
10
and fills the contact hole
50
and recess
52
. Conventional CMP is then carried out to remove metals outside the contact hole
50
.
The above-described prior art process of forming bitline contact hole (CB) has at least two drawbacks. First, although the polysilicon layer
26
that acts as a part of the etching hard mask during the CB etching enables the reduction of the thickness of the CB photoresist and thus improving precision of image transfer, however, the nature of the high diffraction index of the polysilicon layer
26
, which might interfere the mask-wafer alignment, is neutralizing this benefit. Secondly, as shown in
FIG. 5
, recess
52
formed in the peripheral area
21
during the etching of the CB contact hole
50
might lead to M
0
metal circuit open after the tungsten CMP process (dishing effect).
SUMMARY OF INVENTION
Accordingly, it is the primary object of the present invention to provide a semiconductor process to cope with the above-mentioned problems.
It is another object of the present invention to provide a method for precisely making a bitline contact hole (CB) on a substrate, which is capable of eliminating polysilicon hard mask interference during mask-wafer alignment.
According to the claimed invention, a semiconductor process capable of improving alignment accuracy is provided. A semiconductor substrate having thereon an array area and a peripheral area is prepared. The array area comprises a plurality of wordlines and the peripheral area comprises at least one alignment mark. At least one dielectric layer is deposited over the array area and the peripheral area. The dielectric layer covers the wordlines and the alignment mark. A thin silicon nitride layer is then deposited on the dielectric layer. A polysilicon layer is deposited on the thin silicon nitride layer. A first photo resist layer is coated on the polysilicon layer. An opening is then created in the first photo resist layer by conventional lithographic methods. The opening exposes a portion of the polysilicon layer and is located directly above the alignment mark. A portion of the polysilicon layer is etched away through the opening to form an alignment window in the polysilicon layer. The first photo resist layer is then stripped off. Subsequently, a second photo resist layer is coated on the polysilicon layer. The second photo resist layer fills the alignment window in the polysilicon layer. A contact hole opening is created in the second photo resist layer in said array area by conventional lithographic methods. Using the second photo resist layer, polysilicon layer, and the thin silicon nitride layer as an etching hard mask, a contact hole dry etching process is carried out to etch away the polysilicon layer, thin silicon nitride layer, and the dielectric layer through the contact hole opening in the second photo resist layer, thereby forming a contact hole in the array area.
It is advantageous that the dielectric layer directly above the alignment mark in the peripheral area is protected by the thin silicon nitride layer during the contact hole dry etching process.
Other objects, advantages and novel features of the invention will become more clearly and readily apparent from the following detailed description when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 6197481 (2001-03-01), Chang et al.
Chen Yi-Nan
Yang Tung-Liang
Hsu Winston
Nanya Technology Group
Tsai H. Jey
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