Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
1998-10-30
2001-07-17
Follansbee, John A. (Department: 2154)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
C712S002000
Reexamination Certificate
active
06263417
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to techniques for effectively implementing vector operation using a processor chip that is provided with a vector unit, and more specifically to a method of implementing vector operation either within the processor chip or outside this chip depending on vector lengths.
2. Description of the Related Art
When a computer application requires a very large amount of computation to be completed in a reasonable time duration, so-called supercomputers are used. Such computers are needed to handle vectors of data as efficiently as possible. As is known, a vector is a linear array of numbers (elements).
In view of markedly increasing efficiency of vector computation, it is highly desirable to provide a vector unit in addition to a scalar unit on the same processor chip. However, it is not practical to provide the scalar and vector units on the same chip due to a very limited space. Therefore, when the vector data is to be implemented, the processor chip accesses a vector unit provided outside the chip. However, when the vector data, all of which have small vector lengths, are to be processed, it is not desirable to use the vector unit which is provided outside of the processor chip.
SUMMARY OF THE INVENTION
It is therefore an object of the present to provide a method of implementing vector operation using a processor chip which is provided with a vector unit.
In brief, the object is achieved by improved techniques wherein in order to implement vector operation at a higher rate, a processor chip, which is provided with a vector unit in addition to a scalar unit, is prepared. A vector operation mode is first determined, among first and second modes, via which the vector operation is implemented under control of the processor chip. The determination of the vector operation mode is carried out in said processor chip. Thereafter, the vector operation is implemented using the vector unit provided in the processor chip if the vector operation mode is the first mode. On the other hand, the vector operation is implemented using a vector unit, which is provided outside the processor chip, if the vector operation mode is the second mode.
One aspect of the present invention resides in a method of implementing vector operation using a processor chip which is provided with a vector unit, comprising the steps of: determining a vector operation mode, among first and second modes, via which the vector operation is implemented under control of said processor chip, said determination of the vector operation mode being carried out in said processor chip; implementing the vector operation using said vector unit provided in said processor chip if said vector operation mode is the first mode; and implementing the vector operation using a vector unit provided outside said processor chip if said vector operation mode is the second mode.
REFERENCES:
patent: 4128880 (1978-12-01), Cray, Jr.
patent: 5625834 (1997-04-01), Nishikawa
Foley & Lardner
Follansbee John A.
NEC Corporation
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