Method of implementing power-on-reset in power switches

Details Method of implementing power-on-reset in power switches Method of implementing power-on-reset in power switches

2011-08-23

2011-08-23

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

Reexamination Certificate

active

08004321

ABSTRACT:
A power switch circuit and method is provided for having the capability of (1) a power switch circuit having a POR in which the switch is enabled at a predetermined voltage such that the switch is unable to be activated when a minimum lower input voltage is not achieved, to avoid potential conflicts in synchronization and resets with other integrated circuits or chips of an affected system; (2) a POR designed with a delay circuit providing for coordinated stabilization of the power switch before each ON-OFF transition period; (3) using a controlled peaking current in the POR circuit to provide precise RC delay to avoid instability during transition; and (4) a POR providing an externally controlled voltage to power-up other components in the system when energizing of the first component occurs satisfactorily.

REFERENCES:
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patent: 5650673 (1997-07-01), Maeda
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patent: 7671643 (2010-03-01), Dribinsky et al.
patent: 2009/0115390 (2009-05-01), Chen et al.
Wikipedia, “Power-on reset”, http://en.wikipedia.org/wiki/Power-on—reset, Aug. 20, 2007, 1 Page.
Signal Consulting, Inc., “Power-On-Reset”, http://sigcon.com/Pubs/edn/por.htm, Aug. 20, 2007, 2 Pages.
Maxim, “Power-On Reset and Related Supervisory Functions”, http://www.maxim-ic.com/appnotes.cfm/an—pk/3227, Aug. 20, 2007, 7 page.
ACTEL Corporation, “A Power-On Reset (POR) Circuit for Actel Devices”, http://klabs.org/richcontent/fpga—content/ DesignNotes/PowerOnReset.pdf, Sep. 1997, 2 Pages.

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