Method of implementing an accelerated graphics port for a multip

Details Method of implementing an accelerated graphics port for a multip Method of implementing an accelerated graphics port for a multip

1997-12-30

2000-12-05

Chauhan, Ulka J.

Computer graphics processing and selective visual display system

Computer graphic processing system

Interface

345512, 345516, 711206, G06F 1316

Patent

active

061573981

ABSTRACT:
An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions. In a third embodiment of the invention, a plurality of memory controllers implemented on a single chip each contain an AGP and a set of configuration registers identifying a range of addresses that are preferably used for AGP transactions.

REFERENCES:
patent: 4016545 (1977-04-01), Lipovski
patent: 4507730 (1985-03-01), Johnson et al.
patent: 4937734 (1990-06-01), Bechtolsheim
patent: 4969122 (1990-11-01), Jenson
patent: 5109520 (1992-04-01), Knierim
patent: 5121487 (1992-06-01), Bechtolsheim
patent: 5133058 (1992-07-01), Jenson
patent: 5155816 (1992-10-01), Kohn
patent: 5222222 (1993-06-01), Mehring et al.
patent: 5263142 (1993-11-01), Watkins et al.
patent: 5265213 (1993-11-01), Weiser et al.
patent: 5265227 (1993-11-01), Kohn et al.
patent: 5265236 (1993-11-01), Mehring et al.
patent: 5305444 (1994-04-01), Becker et al.
patent: 5313577 (1994-05-01), Meinerth et al.
patent: 5315696 (1994-05-01), Case et al.
patent: 5315698 (1994-05-01), Case et al.
patent: 5321806 (1994-06-01), Meinerth et al.
patent: 5321807 (1994-06-01), Mumford
patent: 5321810 (1994-06-01), Case et al.
patent: 5321836 (1994-06-01), Crawford et al.
patent: 5361340 (1994-11-01), Kelly et al.
patent: 5392393 (1995-02-01), Deering
patent: 5396614 (1995-03-01), Khalidi et al.
patent: 5408605 (1995-04-01), Deering
patent: 5426750 (1995-06-01), Becker et al.
patent: 5440682 (1995-08-01), Deering
patent: 5446854 (1995-08-01), Khalidi et al.
patent: 5465337 (1995-11-01), Kong
patent: 5479627 (1995-12-01), Khalidi et al.
patent: 5491806 (1996-02-01), Horstmann et al.
patent: 5500948 (1996-03-01), Hinton et al.
patent: 5524233 (1996-06-01), Milburn et al.
patent: 5542062 (1996-07-01), Taylor et al.
patent: 5546555 (1996-08-01), Horstmann et al.
patent: 5548739 (1996-08-01), Yung
patent: 5553023 (1996-09-01), Lau et al.
patent: 5584014 (1996-12-01), Nayfeh et al.
patent: 5586283 (1996-12-01), Lopez-Aquado et al.
patent: 5630094 (1997-05-01), Hayek et al.
patent: 5664161 (1997-09-01), Fukushima et al.
patent: 5675750 (1997-10-01), Matsumoto et al.
patent: 5737765 (1998-04-01), Shigeeda
patent: 5778197 (1998-07-01), Dunham
patent: 5778425 (1998-07-01), Shigeeda
patent: 5802603 (1998-09-01), Bains et al.
patent: 5815167 (1998-09-01), Muthal et al.
patent: 5845327 (1998-12-01), Rickard et al.
patent: 5854637 (1998-12-01), Sturges
patent: 5854638 (1998-12-01), Tung
patent: 5861893 (1999-01-01), Sturgess
patent: 5867180 (1999-02-01), Katayama et al.
patent: 5889970 (1999-03-01), Horan et al.
patent: 5892964 (1999-04-01), Horan et al.
patent: 5909559 (1999-06-01), So
patent: 5911051 (1999-06-01), Carson et al.
patent: 5914727 (1999-06-01), Horan et al.
patent: 5930827 (1999-07-01), Sturges
Accelerated Graphics Port Interface Specification, Revision 1.0, Intel Corporation, Jul. 31, 1996.
Intel Advance Information "INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC), " Aug. 1997, 118 pp.
LSI Loogic L64852 Mbus-to-Sbus Controller (M2S) Technical Manual. LSI Logic corporation (1993).

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