Method of high-performance flash memory data transfer

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C365S185110

Reexamination Certificate

active

07366028

ABSTRACT:
A flash memory system including a flash memory device and a controller, operable according to an advanced data transfer mode is disclosed. The flash memory device is operable both in a “legacy” mode, in which read data is presented by the memory synchronously with each cycle of a read data strobe from the controller, and in which input data is latched by the memory synchronously with each cycle of a write data strobe from the controller. In the advanced mode, which can be initiated by the controller forwarding an initiation command to the memory, the flash memory itself sources the read data strobe, and presents data synchronously with both the falling and rising edges of that read data strobe. In the advanced mode, the input data is presented by the controller synchronously with both edges of the write data strobe. The voltage swing of the data and control signals is reduced from conventional standards, to reduce power consumption.

REFERENCES:
patent: 5172338 (1992-12-01), Mehrotra et al.
patent: 5581503 (1996-12-01), Matsubara et al.
patent: 6060916 (2000-05-01), Park
patent: 6094375 (2000-07-01), Lee
patent: 6266273 (2001-07-01), Conley et al.
patent: 6335901 (2002-01-01), Morita et al.
patent: 6621496 (2003-09-01), Ryan
patent: 6747892 (2004-06-01), Khalid
patent: 2003/0031076 (2003-02-01), Widmer et al.
patent: 2003/0043624 (2003-03-01), Roohparvar et al.
patent: 2004/0215996 (2004-10-01), Kanamori et al.
patent: 2005/0207231 (2005-09-01), Kim
patent: 2005/0270891 (2005-12-01), Flach et al.
patent: 95/34030 (1995-12-01), None
“128Mbit DDR SDRAM”, Datasheet K4D261638E, Rev. 1.2 (Samsung, Jul. 2003).
“x32 DDR SDRAM: Device Operation and Timing Diagram” (Samsung).
“DDR SDRAM DIMM: MT4VDDT864A -64MB; MT4VDDT1664A—128MB; MT4VDDT3264A—256MB” (Micron Technology, Inc., 2004).
“CF+ and CompactFlash Specification Revision 3.0” (CompactFlash Association, 2004).
Yoo, “High-Speed DRAM Interface”, Potentials, vol. 20, No. 5 (IEEE, 2001), pp. 33-34.
Nakagome et al., “Sub-1-V Swing Internal Bus Architecture for Future Low-Power ULSI's”, J. Solid State Circ., vol. 28, No. 4 (IEEE, 1993), pp. 414-419.
Lee et al., “A 1 Gbit Synchronous Dynamic Random Access Memory with an Independent Subarray-Controlled Scheme and a Hierarchical Decoding Scheme”, J. Solid State Circ., vol. 33, No. 5 (IEEE, 1998), pp. 779-785.
Ikeda et al., “High-Speed DRAM Architecture Development”, J. Solid State Circ., vol. 34, No. 5 (IEEE, 1999), pp. 685-692.
Kirihata et al., “A 390-mm2, 16-Bank, 1-Gb DDR SDRAM with Hybrid Bitline Architecture”, J. Solid State Circ., vol. 34, No. 11 (IEEE, 1999), pp. 1580-1588.
Yoon et al., “A 2.5-V, 333-Mb/s/pin, 1-Gbit, Double-Data-Rate Synchronous DRAM”, J. Solid State Circ., vol. 34, No. 11 (IEEE, 1999), pp. 1589-1599.
Pilo et al., “An 833-MHz 1.5-W 18-Mb CMOS SRAM with 1.67 Gb/s/pin”, J. Solid State Circ., vol. 35, No. 11 (IEEE, 2000), pp. 1641-1647.
Kuge et al., “A 0.18-um 256-Mb DDR-SDRAM with Low-Cost Post-Mold Tuning Method for DLL Replica”, J. Solid State Circ., vol. 35, No. 11 (IEEE, 2000), pp. 1680-1689.
Yoo et al., “A 1.8-V 200-Mb/s/pin 512-Mb DDR-II SDRAM With On-Die Termination and Off-Chip Driver Calibration”, J. Solid State Circ., vol. 39, No. 6 (IEEE, 2004), pp. 941-951.
Fujisawa et al., “1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 Compatibly Designed 1-Gb SDRAM With Dual-Clock Input-Latch Scheme and Hybrid Multi-Oxide Output Buffer”, J. Solid State Circ., vol. 40, No. 4 (IEEE, Apr. 2005), pp. 862-869.
2GBIT (256M×8 BITS) CMOS NAND E2PROM, part No. TH58NVG1S3AFT05 (Toshiba, 2003).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method of high-performance flash memory data transfer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of high-performance flash memory data transfer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of high-performance flash memory data transfer will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2757317

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.