Coating processes – Coating by vapor – gas – or smoke – Mixture of vapors or gases utilized
Reexamination Certificate
2001-04-26
2003-10-21
Chen, Bret (Department: 1762)
Coating processes
Coating by vapor, gas, or smoke
Mixture of vapors or gases utilized
C427S255290, C427S376100
Reexamination Certificate
active
06635310
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a thermal processing method for conducting a thermal process to a semiconductor wafer or the like, n particular to a thermal processing method suitable for used n forming electrodes of a capacitor.
BACKGROUND OF THE INVENTION
In general, in order to form a semiconductor integrated circuit such as an IC, desired transistors, resistors, capacitors and so on are formed integratedly in a high density by repeating a film-forming process, an etching process, a thermal diffusion process, an oxidation process or the like to a surface of a semiconductor wafer or a glass substrate many times.
Recently, especially, because of a higher integration of a semiconductor unit, each element itself tends to become more minute. For example, in a storing unit such as a DRAM, an area that each cell occupies tends to become smaller and smaller. In order to ensure enough capacitance even if the area becomes smaller, it is enough to make thin a thickness of an insulation layer between capacitor electrodes or to increase a dielectric constant of the insulation layer. However, if the thickness of the insulation layer is made thinner, insulation performance thereof may be deteriorated. In addition, there are various technical problems in making the material higher dielectric.
Thus, a poly-silicon film whose surface has a minutely irregular profile is formed on a surface of an electrode of a capacitor, in order to double or triple a substantial area of the surface that contributes to capacitance. Methods for forming the poly-silicon film whose surface has the irregular profile are for example shown in JP-A-5-304273 and JP-A-7-221034. That is, they are a method of selectively forming an HSG (Hemispherical Grained) poly-silicon film having an irregular surface profile by causing silicon-nucleic crystal to grow up on a surface of a non-doped amorphous silicon film, and a method of directly depositing a Rugged poly-silicon film having an irregular surface profile on an entire surface of a wafer by setting a certain film-forming condition and then selectively etching it in order to form the poly-silicon film only at predetermined portions.
Herein, there is briefly explained a method of forming a poly-silicon film whose surface has an irregular profile such as an HSG poly-silicon film or a rugged poly-silicon film to a desired portion such as an electrode of a capacitor.
FIG. 9
is a process chart for forming an HSG poly-silicon film as a poly-silicon film whose surface has an irregular profile.
In
FIG. 9A
, a channel stopper
2
, a source
4
and a drain
6
are formed on a surface of a semiconductor wafer W consisting of for example a silicon wafer. On surfaces thereof, a layer insulation film
8
consisting of SiO
2
is formed, which may be deposited by using TEOS or the like. A gate electrode
10
is buried in the layer insulation film
8
at a portion between the source
4
and the drain
6
. In addition, a bit line
12
is connected to the drain
6
. The source
4
is connected to a lower electrode
14
that is formed so as to fulfill a contact hole extending through the layer insulation film
8
. An upper end of the lower electrode
14
is formed into a cylindrical circular shape, which enables to make a stack capacitor. For example, the lower electrode
14
is made of a phosphorus-doped amorphous silicon film in which phosphorus atoms have been doped.
Then, in the semiconductor wafer W formed as shown in
FIG. 9A
, as shown in
FIG. 9B
, a non-doped amorphous silicon film
16
is selectively formed on the surface of the lower electrode
14
. In addition, by causing migration by a thermal process under a higher vacuum, silicon-core crystal is selectively formed only on the non-doped amorphous silicon film
16
. Furthermore, as shown in
FIG. 9C
, the core crystal is caused to grow up by atoms in the non-doped amorphous silicon film
16
moving. Thus, the HSG silicon film
18
whose surface has the irregular profile is formed. Herein, sillan or disilane is used as a process gas. A process temperature is for example about 500 to 600° C. Regarding a process pressure, for example when the sillan is used, a partial pressure is 2×10
−3
Torr (2.66×10
−1
Pa) or less.
FIG. 10
is a process chart for forming a rugged poly-silicon film as a poly-silicon film whose surface has an irregular profile. A state shown in
FIG. 10A
is the same as that shown in FIG.
9
A. From the state, as shown in
FIG. 10B
, a rugged poly-silicon film
20
whose surface has an irregular profile is directly caused to deposit on an entire surface of the semiconductor wafer W by a predetermined film-forming process. In the case, the rugged poly-silicon film
20
is deposited on the entire surface of the wafer. After that, by a pattern etching process, as shown in
FIG. 10C
, the rugged poly-silicon film
20
at unnecessary portions is removed so that the rugged poly-silicon film
20
only on the surface of the lower electrode
14
is left.
As shown in
FIGS. 9 and 10
, after the HSG poly-silicon film
18
whose surface has the irregular profile or the rugged poly-silicon film
20
whose surface has the irregular profile is formed on the surface of the lower electrode
14
, an annealing process is conducted at a predetermined temperature. Thus, phosphorus atoms diffuse from the lower electrode
14
being a lower phosphorus-doped amorphous silicon film to the core poly-silicon film
18
or
20
. Thus, the core poly-silicon film
18
or
20
becomes a part of the lower electrode. Therefore, the surface area of the lower electrode
14
can be substantially enlarged because of irregularity of the surface of poly-silicon film
18
or
20
in which phosphorus has been doped as described above.
After that, as shown in
FIG. 11
, a capacitance insulating film
22
consisting of SiO
2
or the like is formed on a surface side of the lower electrode
14
. Then, a capacitor is formed by making a patterning-processed upper electrode
24
.
Herein, in order to cause the HSG poly-silicon film
18
or the rugged poly-silicon film
20
to sufficiently serve as the part of the lower electrode, an enough amount of phosphorus atoms has to be diffused and doped from the lower electrode
14
being the lower phosphorus-doped amorphous silicon film. If the diffusions of the phosphorus atoms are not enough, a depletion layer may be generated, which may cause reduction of the capacitance. A state of the case is shown in FIG.
12
.
FIG. 12
is a graph showing a capacitance change when positive and negative voltages are applied to the capacitor produced as described above. As clearly seen from the graph, the capacitance remarkably reduces when the voltage is negative, which is undesired in performance as the capacitor.
As a measure thereto, in the case of the HSG poly-silicon film, it may be thought to make the thickness of the film thinner. However, if the thickness is too thin, the irregularity of the surface of the HSG film can not appear. In addition, it may be also thought to increase phosphorus density in the lower electrode
14
. However, if the phosphorus density is too high, it becomes difficult to form the HSG film by migration.
As another measure, ionizing phosphorus atoms and directly implanting the ionized phosphorus atoms to the silicon film
18
or
20
with an implantation unit are carried out. However, in the case, the silicon film
18
or
20
may be heavily damaged by the ion implantation. In addition, in the case of the lower electrode
14
having the complicated configuration as shown in
FIGS. 9 and 10
, it is difficult for the ions to reach side wall portions thereof. That is, it is difficult to implant the phosphorus atoms at even ion density.
In addition, doping phosphorus atoms in the poly-silicon film
18
or
20
is also carried out by an anneal process in a POCl
3
atmosphere. However, in the case, if an annealing temperature is not set at 800° C. or more, the phosphorus atoms are not doped sufficiently. However, if the semiconductor wafer itself is exposed to suc
Fujita Yoshiyuki
Kato Hitoshi
Tojo Yukio
Tsuda Toshitake
Chen Bret
Smith , Gambrell & Russell, LLP
Tokyo Electron Limited
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