Method of gettering using doped SOG and a planarization techniqu

Details Method of gettering using doped SOG and a planarization techniqu Method of gettering using doped SOG and a planarization techniqu

1995-03-21

1999-02-09

Niebling, John F.

Semiconductor device manufacturing: process

Gettering of substrate

By layers which are coated, contacted, or diffused

438143, 438760, 438763, 438782, 438787, H01L 21322

Patent

active

058693882

ABSTRACT:
A method is provided for a planar surface of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A gate electrode is formed over a substrate having source/drain regions adjacent to the gate electrode and in the substrate. A silicon dioxide layer is formed over the gate electrode and a portion of the substrate not covered by the gate electrode. A first phosphorous doped spin-on-glass layer is formed over the silicon dioxide layer, wherein the spin-on-glass is doped to a concentration sufficient to facilitate gettering of charge mobile ions. An opening is then formed in the spin-on-glass layer and the silicon dioxide layer exposing a portion of the source drain region.

REFERENCES:
patent: 4828629 (1989-05-01), Ikeda et al.
patent: 4920072 (1990-04-01), Keller et al.
patent: 5424570 (1995-06-01), Sardella et al.
Allied Signal Technologies Product Bulletin, "Accuglass P-XXY A Series Phosphosilicate Spin-On Glasses".
Allied Signal Technologies Product Bulletin; "Accuglass P-XXY A Series Phosphosilicate Spin-On Glasses"; Nov. 1988.
Allied Signal Technologies Product Bulletin; "Accuglass P-TTY A Series Phosphosilicate Spin-On Glasses"; May 1992.

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