Method of generating test patterns for logic network devices

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371 20, 371 25, 324 73R, G01R 3128

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046960066

ABSTRACT:
Nodes and paths for connecting the nodes are used to form a model of at least one logic network. Next, all paths for connecting nodes in the logic network are traced, and the nodes and connecting path segments are sensitized and justified. The sensitizing patterns, when generating test patterns for a sequential circuit wherein the output is a function of a time sequence of inputs, may include a time sequence of sensitizing or input patterns for testing a single path through the network.

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M. Kawai, H. Shibano, S. Funatsu, S. Kato, T. Kurobe, K. Ookawa & T. Sasaki, "A High Level Test Pattern Generation Algorithm", 1983.

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