Static information storage and retrieval – Addressing – Sequential
Reexamination Certificate
2001-11-13
2002-10-15
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Addressing
Sequential
C365S230030
Reexamination Certificate
active
06466512
ABSTRACT:
BACKGROUND
The present invention relates to information storage devices. More specifically, the present invention relates to address logic for solid state memory.
Portable devices such as PDAs, handheld computers, digital cameras and digital music players include memory for storing data, digital images and MP3 Files. Different types of memory are available for these portable devices. Conventional memory types include flash memory, mini-hard drives, mini-compact discs, and magnetic tape. However, each of these memory types has one or more of the following limitations: large physical size, low storage capacity relatively high cost, poor robustness, slow access time and high power consumption.
Solid state diode-based OTP memory is disclosed in assignee's U.S. Ser. No. 09/875,356 filed Jun. 5, 2001. Compared to the conventional memory, the diode-based memory has a high shock tolerance, low power consumption, fast access time, moderate transfer rate and good storage capacity. The diode-based memory can fit into a standard portable interface (e.g., PCMCIA, CF) of a portable device.
In a diode-based memory device having multiple levels, each level has main memory and address logic (unlike conventional solid state memory such as DRAM). The address logic of the diode-based memory device is programble. The address logic may be programmed after each level has been fabric. Since no masking is required, physical processing is simplified.
Increasing memory capacity is a continuing goal of memory manufacturers. As memory capacity is increased, however, the number of address lines and memory lines is also increased. In turn, address configurations are made longer to accommodate the increase in address lines, and the numbs of address configurations is increased to accommodate the increase in memory lines.
Efficient generation of the address configurations is needed.
SUMMARY
According to one aspect of the present invention, a method involves the use of a sequence of address configurations covering L memory lines and n address lines. The method includes forming L blocks. A most significant column of each block is filled with the sequence such that the most significant column of each block contains the same unshifted sequence. A least significant column of each block is filled with the sequence such that entries in the least significant column of the blocks are shifted cyclically. The L blocks contain address configurations for L
2
memory lines and 2
n
address lines.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompany drawings, illustrating by way of example the principles of the present invention.
REFERENCES:
patent: 4092665 (1978-05-01), Saran
patent: 6134173 (2000-10-01), Cliff et al.
Hogan Josh N.
Roth Ron M.
Hewlett -Packard Company
Hoang Huan
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