Data processing: artificial intelligence – Neural network – Structure
Reexamination Certificate
2006-11-28
2006-11-28
Vincent, David (Department: 2129)
Data processing: artificial intelligence
Neural network
Structure
C706S039000
Reexamination Certificate
active
07143073
ABSTRACT:
The invention relates to generating a test suite of instructions for testing the operation of a processor. A fuzzy finite state machine with a plurality of states2and transitions4determined by weights W1, W2. . . W10is used to generate a sequence of instructions. The weights determine the next state as well as an instruction and operands for each state. The weights may be adapted based on the generated sequence and further sequences are generated.
REFERENCES:
patent: 4827521 (1989-05-01), Bahl et al.
patent: 5500941 (1996-03-01), Gil
patent: 5526465 (1996-06-01), Carey et al.
patent: 5606646 (1997-02-01), Khan et al.
patent: 5623499 (1997-04-01), Ko et al.
patent: 5724504 (1998-03-01), Aharon et al.
patent: 5828812 (1998-10-01), Khan et al.
patent: 5918037 (1999-06-01), Tremblay et al.
patent: 5943659 (1999-08-01), Giles et al.
patent: 6134675 (2000-10-01), Raina
patent: 6269457 (2001-07-01), Lane
patent: 6523151 (2003-02-01), Hekmatpour
patent: 6577982 (2003-06-01), Erb
patent: 6944848 (2005-09-01), Hartman et al.
patent: 2003/0233600 (2003-12-01), Hartman et al.
“A Markov chain modeling technique for evaluating pipelined processor designs”, by Unwala, I.H.; Cragon, H.G.; Circuits and Systems, 1994, Proceedings of the 37th Midwest Symposium on vol. 1, Aug. 3-5, 1994 pp. 319-322 vol. 1.
“Design evaluation of pipelined processors using finite state machine analysis with Markov chains”, by Unwala, I.H.; Cragon, H.G.; Economics of Design, Test, and Manufacturing, 1994. Proceedings, Third Int'l Conf on the May 16-17, 1994 pp. 147-151.
“Pipelined Processor Modeling with Finite Homogeneous Discrete-time Markov Chain”, Ph D. Dissertation by Ishaq Hasanali Unwala, May 1998.
“Fuzzy Markov chains”, by Buckley, J.J.; Feuring, T.; Hayashi, Y.; IFSA World Congress and 20th NAFIPS International Conference, 2001. Joint 9th Jul. 25-28, 2001 pp. 2708-2711 vol. 5.
“An Introduction to Hidden Markov Models”, by Rabiner, L.R.; Juang, B.H.; ASSP Magazine, IEEE [see also IEEE Signal Processing Magazine] vol. 3, Issue 1, Jan. 1986 pp. 4-16.
Chapter 4: Markov Models, by Christopher Manning & Hinrich Schutze, DRAFT! c fl1996.
“Compacting Regression-Suites On-The-Fly”, by Buchnik, E.; Ur, S.; Software Engineering Conference, 1997. Asia Pacific . . . and International Computer Science Conference 1997. APSEC '97 and ICSC '97. Proceedings Dec. 2-5, 1997 pp. 385-394.
“Probabilistic Sequence Models”, http://globin.cse.psu.edu/courses/fall2002/prob.pdf.
Model Based Testing, DACS Gold Practices Website.
Lecture 7. Inf1A: Probabilistic Finite State Machines and Hidden Markov Models. http://www.inf.ed.ac.uk/teaching/courses/inf1/cl
otes/Comp7.pdf.
“Design Evaluation of Pipelined Processors using Finite State Machine Analysis with Markov Chains”, Unwala, I.H.; Cragon, H.G.; Economics of Design, Test, & Manufacturing, 1994. Proceedings, 3rd Intl Conf on May 16-17, 1994. pp. 147-151.
“Functional Verification Methodology of Chameleon Processor”, Casaubieilh, F.; McIsaac, A.; Benjamin, M.; Bartley, M.; Pogodalla, F.; Ro, F.; Design Automation Conference Proceedings 1996, 33rd, Jun. 3-7, 1996. pp. 421-426.
“Verification of Processor Microarchitectures”, Shen, J.; Abraham, J.A.; VLSI Test Symposium, 1999. Proceedings 17th IEEE Apr. 25-29, 1999. pp. 189-194.
“High-level test generation for Design Verification of Pipelined Microprocessors”, Van Campenhout, D.; Mudge, T.; Hayes, J.T.; Design Automation Conference, 1999. Proceedings, 36th, Jun. 21-25, 1999. pp. 185-188.
“A New Method for On-line State Machine Observation for Embedded Microprocessors”, Pflanz, M.; Galke, C.; Vierhaus, H.T.; High-Level Design Validation & Test Workshop, 2000. Proceedings. IEEE International Nov. 8-10, 2000. pp. 34-39.
Eric Bonabeau and Guy Theraulaz, “Swarm Smarts”,Scientific American, pp. 73-79, Mar. 2000.
Sterne Kessler Goldstein & Fox PLLC
Tran Mai T.
Vincent David
LandOfFree
Method of generating a test suite does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of generating a test suite, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of generating a test suite will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3697892