Method of generating a restricted inline resistive fault...

Details Method of generating a restricted inline resistive fault... Method of generating a restricted inline resistive fault...

2008-12-17

2011-11-08

Bui, Bryan (Department: 2857)

Data processing: measuring, calibrating, or testing

Testing system

Including program set up

C324S762020

Reexamination Certificate

active

08055467

ABSTRACT:
A method of generating an IRF pattern for testing an IC and a test pattern generator are disclosed. In one embodiment, the method includes: (1) identifying a path of the integrated circuit for inline resistive fault pattern generation, (2) determining if the path is a minimal slack path of the IC and (3) generating, when the path is the minimal slack path, a restricted inline resistive fault pattern for the path using only a capture polarity having a minimal inherent margin.

REFERENCES:
patent: 2005/0240887 (2005-10-01), Rajski et al.
patent: 2008/0211531 (2008-09-01), Gattiker et al.

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