Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
2006-05-02
2006-05-02
Rodriguez, Paul L. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C703S002000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07039573
ABSTRACT:
The total resistance value of a coupling portion between first and second circuits is used as the resistance value of a load model; one-half of the total capacity value of the coupling portion is used as each coupling capacity value of the load model; the sum of one-half of the total earth capacity value of the coupling portion and the total capacity value of a non-coupling portion near a first circuit driver is used as the earth capacity value of the load model at a point near the first circuit driver; and the sum of one-half of the total earth capacity value of the coupling portion and the total capacity value of a non-coupling portion farther from the first circuit driver than the coupling portion is used as the earth capacity value of the load model at a point remote from the first circuit driver.
REFERENCES:
patent: 6353917 (2002-03-01), Muddu et al.
patent: 6378109 (2002-04-01), Young et al.
patent: 6405348 (2002-06-01), Fallah-Tehrani et al.
patent: 6493853 (2002-12-01), Savithri et al.
patent: 6925624 (2005-08-01), Komoda
patent: 2002/0060572 (2002-05-01), Komoda
patent: 4-337869 (1992-11-01), None
patent: 6-34665 (1994-02-01), None
Ye, Lun et al. “Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs.” Proc. DAC in Europe. 1999.
Gross, Paul et al. “Determination of Worst-Case Aggressor Alignment for Delay Calculation.” Proc. 1998 IEEE/ACM Int'l Conf. on CAD. 1998. pp. 212-219.
Kim, S.Y. et al. “An Efficient Methodology for Extraction and Simulation of Transmission Lines for Application Specific Electronic Modules.” Proc. of the 1993 IEEE/ACM Int'l Conf. on CAD. 1993. pp. 58-65.
ARCADIA User's Manual. Version 1.1. Feb. 1995.
Cong, Jason et al. “Improved Crosstalk Modeling for Noise Constrained Interconnect Optimization.” Proc. IEEE/ACM TAU. Dec. 4-5, 2000. Austin, Texas.
Cong, Jason et al. “Improved Crosstalk Modeling with Applications to Noise Constrained Interconnect Optimization.” Proc. SRC Techcon Conf., Sep. 21-23, 2000. Phoenix, Arizona.
David Z. Pan's Patents and Publications. http://www.ece.utexas.edu/˜dpan/publications/ Printed on Jun. 17, 2005.
Blackwell, G.R. “Chapter 5: Circuit Boards.” The Electronic Packaging Handbook. CRC Press LLC. 2000. Boca Raton, FL.
Majumdar, A. et al. “Ground Bounce Considerations in DC Parametric Test Generation Using Boundary Scan.” Proc. 16th IEEE VLSI Test Symposium, 1998. Apr. 26-30, 1998. pp. 86-91.
D'Amore, M. et al. “A New Efficient Procedure for the Transient Analysis of Dissipative Power Networks with Non-linear Loads.” IEEE Transactions on Power Delivery. Jan. 1996. vol. 11, Issue 1, pp. 533-539.
Buchanan & Ingersoll PC
Renesas Technology Corp.
Rodriguez Paul L.
Sharon Ayal
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