Method of forming well for CMOS imager

Semiconductor device manufacturing: process – Making device or circuit responsive to nonelectrical signal

Reexamination Certificate

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C438S224000

Reexamination Certificate

active

06897082

ABSTRACT:
A well region of a first conductivity type located in a substrate of the first conductivity type and below about half the channel length of an electrically active portion of a transistor gate is disclosed. The well region is laterally displaced from a charge collection region of a second conductivity type of a pinned photodiode.

REFERENCES:
patent: 5877049 (1999-03-01), Liu et al.
patent: 6326219 (2001-12-01), Markle et al.
patent: 6768149 (2004-07-01), Mann et al.
patent: 6794281 (2004-09-01), Madhukar et al.

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