Method of forming vias in silicon carbide and resulting...

Semiconductor device manufacturing: process – Forming schottky junction – Combined with formation of ohmic contact to semiconductor...

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S716000, C438S707000, C438S712000, C438S730000, C438S740000, C257SE21603, C257SE31049, C257SE29104, C257SE21182

Reexamination Certificate

active

07125786

ABSTRACT:
A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device in epitaxial layers on a surface of a silicon carbide substrate and with at least one metal contact for the device on the uppermost surface of the epitaxial layer. The opposite surface of the substrate is then ground and polished until it is substantially transparent. The method then includes masking the polished surface of the silicon carbide substrate to define a predetermined location for at least one via that is opposite the device metal contact on the uppermost surface of the epitaxial layer and etching the desired via in steps. The first etching step etches through the silicon carbide substrate at the desired masked location until the etch reaches the epitaxial layer. The second etching step etches through the epitaxial layer to the device contacts. Finally, metallizing the via provides an electrical path from the first surface of the substrate to the metal contact and to the device on the second surface of the substrate.

REFERENCES:
patent: 4771017 (1988-09-01), Tobin et al.
patent: 4866507 (1989-09-01), Jacobs et al.
patent: 4874500 (1989-10-01), Madou et al.
patent: 4951014 (1990-08-01), Wohlert et al.
patent: 4966862 (1990-10-01), Edmond
patent: 5185292 (1993-02-01), VanVonno et al.
patent: 5187547 (1993-02-01), Niina et al.
patent: 5264713 (1993-11-01), Palmour
patent: 5279888 (1994-01-01), Nii
patent: 5343071 (1994-08-01), Kazior et al.
patent: 5406122 (1995-04-01), Wong et al.
patent: 5449953 (1995-09-01), Nathanson et al.
patent: 5539217 (1996-07-01), Edmond et al.
patent: 5662770 (1997-09-01), Donohoe
patent: 5672546 (1997-09-01), Wojnarowski
patent: 5807783 (1998-09-01), Gaul et al.
patent: 5914508 (1999-06-01), Varmazis et al.
patent: 5935733 (1999-08-01), Scott et al.
patent: 5939732 (1999-08-01), Kurtz et al.
patent: 5963818 (1999-10-01), Kao et al.
patent: 6020600 (2000-02-01), Miyajima et al.
patent: 6087719 (2000-07-01), Tsunashima
patent: 6114768 (2000-09-01), Gaul et al.
patent: 6128363 (2000-10-01), Shoki et al.
patent: 6221537 (2001-04-01), Thompson et al.
patent: 6225651 (2001-05-01), Billon
patent: 6297100 (2001-10-01), Kumar et al.
patent: 6316826 (2001-11-01), Yamamoto et al.
patent: 6515303 (2003-02-01), Ring
patent: 2001/0023964 (2001-09-01), Yifeng Wu et al.
patent: 2003/0003724 (2003-01-01), Uchiyama et al.
patent: 2004/0241970 (2004-12-01), Zoltan Ring
patent: 0663693 (1995-07-01), None
patent: 0887854 (1998-12-01), None
patent: 410229074 (1998-08-01), None
Ralph E. Williams, Gallium Arsenide Processing Techniques, 1984, pp. 346-351, Artech House, Inc., Dedham, MA.
J. J. Wang, et al., Low Bias Dry Etching of SiC and SiCN in ICP NF3 Discharges, Mat Res. Soc. Symp. Proc., 1998, vol. 512, Materials Research Society.
J. R. Flemish and K. Xie, Profile and Morphology Control during Etching of SiC Using Electron Cyclotron Resonant Plasmas, J. Electrochem Soc., Aug. 1996, pp. 2620-2623, vol. 143, No. 8, The Electrochem Society, Inc.
G. McDaniel, et al., Comparison of dry etch chemistries for SiC, J. Vac. Sci. Technol., May/Jun. 1997, pp. 885-889, A 15(3), American Vacuum Society.
J. J. Wang, et al., Low Damage, Highly Anisotropic Dry Etching of SiC, IEEE, 1998, pp. 10-14.
J. J. Wang, et al., Inductively coupled plasma etching of bulk 6H—SiC and thin-film SiCN in NF3 chemistries, J. Vac. Sci. Technol., Jul./Aug. 1998, pp. 2204-2209, A 16(4).
Lihui Cao, et al., Etching of SiC Using Inductively Coupled Plasma, J. Electrochem Soc., Oct. 1998, pp. 3609-3612, vol. 145, No. 10, The Electrochemical Society, Inc.
J. Hong, et al., Plasma Chemistries for High Density Plasma Etching of SiC, Journal of Electronic Materials, 1999, pp. 196-201, vol. 28, No. 3.
P. Leerungnawarat, et al., Via-hole etching for SiC, J. Vac. Sci. Technol., Sep./Oct. 1999, pp. 2050-2054, B 17(5), American Vacuum Society.
Cho, et al.; High density plasma via hole etching in SiC; 47th International Symposium of the American Vacuum Society, Boston, MA, vol. 19, No. 4, pt. 1-2, pp. 1878-1881; J. Vac. Sci. Technol., Jul.-Aug. 2001, AIP for American Vacuum Soc., USA.
P. Chabert, et al.; High rate etching of 4H—SiC using a SF/sub 6//0/sub2/helicon plasma; Applied Physics Letters, Apr. 17, 2000, AIP, USA, vol. 76, No. 16, pp. 2310-2312.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method of forming vias in silicon carbide and resulting... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming vias in silicon carbide and resulting..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming vias in silicon carbide and resulting... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3707187

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.