Method of forming via-holes in multilayer circuit boards

Details Method of forming via-holes in multilayer circuit boards Method of forming via-holes in multilayer circuit boards

2000-11-22

2003-10-14

Beck, Shrive P. (Department: 1763)

Etching a substrate: processes

Forming or treating electrical conductor article

C216S017000, C216S018000

Reexamination Certificate

active

06632372

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method of manufacturing a multilayer circuit board, and more particularly to a method of forming via-holes in a multilayer circuit board.
2. Description of the Prior Art
Current market trends in the electronics industry are to decrease size and weight of circuit boards while increasing its speed, capability and interconnection density. The formation of via-holes in the interconnecting layers of multilayer circuit boards is a key factor in this development.
A number of advancements have been aimed at forming via-holes in the interconnecting layers of a multilayer circuit board by laser, photosensitive insulating layers or plasma drilling. For example, U.S. Pat. No. 5,948,280 discloses the use of not reinforced binders by laser or plasma drilling to form via-holes in multilayer circuit boards. In the case when a laser is used, via-holes are formed one by one, consequently its speed is relatively slow and is prone to residue problems. On the other hand, by way of plasma drilling, the process and the shapes of via-holes are hard to control.
Moreover, U.S. Pat. No. 5,914,216 teaches the usage of a photosensitive resin composition by a photolithographic technique to form via-holes. The photosensitive resin contains high exposing energy, therefore it is not user-friendly nor environmental-friendly. As for U.S. Pat. No. 5,451,721, photosensitive resin material is used for insulating layers. By photolithographic technique and conventional copper plating technique, high interconnection density is achieved. However, photosensitive material and solvents are necessary for the image development process, consequently pollution and safety issues will arise.
As for etching, U.S. Pat. No. 5,200,026 teaches the usage of the photo-imaging property of positive photoresists and by way of photolithographic technique to manufacture via bumps to interconnect upper layers and lower layers of circuit boards. However, it is hard to control the size of via bumps to achieve the required accuracy.
U.S. Pat. No. 5,092,032 discloses the structure of photoresist layers as a wiring layer and an electronically connected vias and the formation of a landless inner connection layer by via bumps. In this method, the via bumps are formed by plating, which is more suitable for connecting power source layer or ground layer. As a result, this is not ideal for signal transmitting.
SUMMARY OF THE INVENTION
The primary object of the invention is to provide a method for forming via-holes in multilayer circuit boards, wherein many via-holes can be formed simultaneously, hence the speed of forming via-holes is improved. Furthermore, the usage of material is not restricted.
To achieve the above-mentioned objects, the invention discloses a method for forming via-holes in multilayer circuit boards, comprising: forming covering substances at predetermined spots in a multilayer circuit board; applying an insulation layer upon the multilayer circuit board and thereafter uncovering the covering substances; and removing said covering substances to obtain via-holes.
According to the invention, via-holes are formed in one operation, consequently the speed is increased. Furthermore, the material is chosen from either photo-sensitive material or non photo-sensitive material, which allows more freedom in application


REFERENCES:
patent: 5092032 (1992-03-01), Murakami
patent: 5200026 (1993-04-01), Okabe
patent: 5451721 (1995-09-01), Tsukada et al.
patent: 5914216 (1999-06-01), Amou et al.
patent: 5948280 (1999-09-01), Namgung

Affiliated with

Also associated with

Rating

Method of forming via-holes in multilayer circuit boards does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming via-holes in multilayer circuit boards, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming via-holes in multilayer circuit boards will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3171885