Method of forming vertically integrated current source

Details Method of forming vertically integrated current source Method of forming vertically integrated current source

1985-09-24

1987-09-01

Hearn, Brian E.

Fishing, trapping, and vermin destroying

156643, 357 55, 148DIG50, 148DIG131, 437225, 437203, H01L 21302, H01L 21441

Patent

active

046898719

ABSTRACT:
A current source MOSFET is fabricated by forming a trench (36) in an n++ drain (source) region (32) and extending below the trench (36). A gate oxide layer (40) is disposed on the sidewalls of the trench (36) and a conductive region (38) formed in the bottom of the trench (36). A gate-to-source (gate-to-drain) contact (49) is then formed in the trench (36) and then a drain (source) contact (58) formed. The vertical gate structure defines a vertical channel region on all sides of the trench (36) to allow a wider devive to be fabricated in a smaller overall silicon area.

REFERENCES:
patent: 3920482 (1975-11-01), Russel
patent: 4116720 (1978-09-01), Vinson
patent: 4353086 (1982-10-01), Jaccodine et al.
patent: 4476622 (1984-10-01), Cogan
patent: 4502914 (1985-03-01), Trumpp et al.
patent: 4520552 (1985-06-01), Arnould et al.
Chang, "Vertical FET Random Access Memories with Deep Trench Isolation", vol. 22, No. 8B, Jan. 1980, pp. 3683-3687.

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