Method of forming tunneling diffusion barrier for local intercon

Details Method of forming tunneling diffusion barrier for local intercon Method of forming tunneling diffusion barrier for local intercon

1991-08-06

1993-01-19

Quach, T. N.

Fishing, trapping, and vermin destroying

437 43, 437190, 437241, 437193, H01L 21283

Patent

active

051806886

ABSTRACT:
A semiconductor device is described in which a conductive layer overlaps a dielectric layer forming a composite electrical device deposited over selected portions of a semiconductor substrate chemically isolating the conductive layer portion of the composite electrical device from the substrate, thereby preventing diffusion of dopant material through the dielectric layer into and out of the conductive layer while simultaneously allowing for tunneling of electrons through the dielectric layer to and from the conductive layer and the semiconductor substrate.

REFERENCES:
patent: 4562640 (1986-01-01), Widmann et al.
patent: 4641173 (1987-02-01), Malhi et al.
patent: 4755480 (1988-07-01), Yau et al.
patent: 4782380 (1988-11-01), Shankar et al.
patent: 4786612 (1988-11-01), Yau et al.
patent: 4935378 (1990-06-01), Mori
patent: 4935801 (1990-06-01), McClure et al.
patent: 4935804 (1990-06-01), Ito et al.
patent: 4937643 (1990-06-01), Deslauriers et al.
patent: 4939567 (1990-07-01), Kenney
patent: 4948755 (1990-08-01), Mo
patent: 5065225 (1991-11-01), Bryant et al.
Article in IEEE Transaction on Electron Devices, vol. 37, No. 8, Aug. 1990, titled "Thickness Limitation of SiO.sub.2 Gate Dielectrics for MOS ULSI" by Peter J. Wright, et al.
Article in S. Pantelides, 1978, pp. 47-51, "Physics of SiO.sub.2 and its Interfaces," published by Pergamon Press in an article by M. Av-Ron et al titled The Nature of Electron Tunneling in SiO.sub.2.
Text in R. Muller et al, "Device Electronics for Integrated Circuits," Section 3.4 Junction Breakdown, pp. 135-136, published by John Wiley & Sons (1977).
Article in 1987 ECS Symposium, pp. 215-226, by L. Do Thanh, et al, titled "Electrical Properties of Thin LPCVD Institute of Semiconductor Electronics".
Article in Electronics Review, Jan. 3, 1980, pp. 39-40, titled "Thin-film devices on silicon chip withstand up to 500.degree. C.", by Rober Allan.

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