Method of forming trench isolation in an integrated circuit

Details Method of forming trench isolation in an integrated circuit Method of forming trench isolation in an integrated circuit

1984-10-15

1987-10-20

Hearn, Brian E.

Fishing, trapping, and vermin destroying

H01L 2122, H01L 21302

Patent

active

047004649

ABSTRACT:
A semiconductor integrated circuit device is provided with polycrystalline silicon filling U-grooves etched in a semiconductor substrate to form isolation regions which prevent any short-circuiting between the polycrystalline silicon and electrodes or wiring formed on the semiconductor substrate. A silicon dioxide film is formed within the U-grooves, and a silicon nitride film and a silicon dioxide film are further formed thereon. The silicon nitride film has a high hardness which suppresses the development of crystal defects in the peripheral active regions due to the expansion of the surface of the polycrystalline silicon when it is oxidized. When the surface of the polycrystalline silicon is oxidized, the oxidation proceeds along the oxide film over the nitride film, so that the whole of the oxide film is formed thickly. Therefore, the silicon nitride film and the silicon dioxide film are provided with an increased margin against the etching used for forming contact holes.

REFERENCES:
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patent: 4396460 (1983-08-01), Tamaki et al.
patent: 4528047 (1985-07-01), Beyer et al.
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Takemoto et al., "A Vertically Isolated Self Aligned Transistor-VIST", IEEE Trans. Elec. Devices, vol. ED-29, No. 11, Nov. 1982, pp. 1761-1765.
Antipov, "Prevention of Birdsbeak Formation", IBM Tech. Disc. Bull., vol. 23, No. 11, Apr. 1981, pp. 4917-4919.

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