Method of forming trench isolation having polishing step and met

Fishing – trapping – and vermin destroying

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437228, H01L 2176

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active

054985650

ABSTRACT:
A method of forming trench isolation including a burying step of burying trenches by a deposition means for conducting etching and deposition simultaneously and a polishing step of flattening a burying material by polishing is conducted by disposing an isotropic etching step, a multi-layered etching stopper and a protrusion unifying structure. Polishing can be attained with satisfactory flatness uniformly or with no polishing residue even in a portion to be polished in which the etching stopper layer is distributed unevenly. The method can be applied to manufacture of a semiconductor device or the like.

REFERENCES:
patent: 5182221 (1993-01-01), Sato
Machida, K., et al, "SiO.sub.2 Planarization . . . Interconnections", J. Vac. Sci. Tech. vol. 4 No. 4 Jul. 8, 1986 pp. 818-821.
Wolf, S., Silicon Processing For The VLSI Era, vol. 2 Process Integration, Lattice Press .COPYRGT.1990, pp. 222-224 & 238-239.
Tetsuo Gocho et al., "Trench Isolation Technology for 0.35 .mu.m Device by Bias ECR CVD," pp. 87-88 May 1992.
Wolf, S., Silicon Processing for the VLSI Era: Process Technology vol. 1, Lattice Press, 1986 pp. 529-533.
Wolf, S., Silicon Processing for the VLSI Era, Process Integration, vol. 2, 1990, Lattice Press (pp. 225-229).

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