Method of forming trench isolation

Details Method of forming trench isolation Method of forming trench isolation

2000-03-30

2002-03-05

Utech, Benjamin L. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S700000, C438S706000, C438S745000

Reexamination Certificate

active

06352928

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method of forming trench isolation and a method of producing a semiconductor device. The present invention can be utilized for producing various semiconductor devices containing a concave portion burying process step and a subsequent planarization CMP process step, particularly for producing those semiconductor devices which have trench isolation (trench type device isolation).
The present invention can be utilized also for producing semiconductor devices that call for a burying process step, that buries concave portions defined by a plurality of convex regions (i.e. defined between convex regions), by a burying material, and a CMP process step for planarizing the burying material layer formed on each convex region.
2. Description of Related Art
The size of integrated circuits has become smaller and smaller. Therefore, it has become all the more necessary to arrange those components which constitute an integrated circuit adjacent to one another in a limited space. Studies in general have been directed to improve the density of an active region per unit area of a semiconductor substrate. For this reason, effective isolation between circuits has become more important.
The shape of a shallow trench, which is formed by etching a semiconductor substrate to form a trench and charging the trench by an insulating material, such as silicon dioxide, has been employed in existing integrated circuit technologies. The region in which this isolation is defined is generally referred to as “shallow trench isolation (STI)”. If this STI region is utilized, the active region of an integrated circuit can be formed substantially in an arbitrary size. Therefore, the size of the STI region varies over a broad range.
Particularly when a shallow trench the width of which varies over a broad range is used for complicated topography of existing integrated circuits, the problem of non-uniform burying of an oxide often arises when the oxide is uniformly charged into the trench. To cope with this problem, a method that charges an insulation material into the STI region, and a large number of planarization methods that planarize the resulting structure to uniform topography, have been developed.
The following methods are known for forming flat trench isolation, for example.
First, a thin silicon dioxide film and a thin silicon nitride film are formed on a silicon substrate. Trenches are then formed in the silicon substrate by etching through a photolithography step. Silicon dioxide is deposited as a burying material. When this deposited silicon dioxide is polished, flat trench isolation can be formed because the silicon nitride film having a lower polishing rate than silicon dioxide functions as a stopper layer.
If convex regions having a small width exist in a coarse and fine distribution, the coarse regions turn to a convex shape and cannot be planarized. This problem can be solved if a dummy pattern having the same convex shape is inserted. When the dummy pattern is inserted, this portion becomes an active region. It increases a capacity and eventually results in the problem that a device speed gets slow. Therefore, the dummy pattern cannot be inserted from time to time.
If any convex regions having a wide top surface exist, silicon dioxide as the burying material remains at the center of the wide top surface of the convex regions and result in the formation of particles. These problems are known in the art, and are explained in Japanese Unexamined Patent Publication No. HEI 5(1994)-275527.
Therefore, Japanese Unexamined Patent Publication No. HEI 5(1994)-275527 employs deposition means called “bias ECR-CVD process” that executes concurrently etching and deposition, as a deposition method of the burying material.
This deposition method can deposit the burying material layer
23
made of silicon dioxide and having a trapezoidal section that is thicker than on the top surfaces of the narrow convex regions (A and B), on the top surface of the wide convex region
9
as shown in FIG.
5
(
a
). On the other hand, this method can deposit the burying material layer
24
having a triangular section on the top surface of the convex regions having a small width.
According to this Publication, the burying material layer on the wide convex region is isotropically etched using a resist mask after the deposition by the bias ECR-CVD process. As a result of this etching, the shape of the burying material layer on the wide convex region is made similar to the triangular shape on the convex regions having a small width. Only the triangular portion is polished and is then etched back for planarization (see Example 1 and FIG. 1 of Japanese Unexamined Patent Publication No. HEI 5(1994)-275527).
This Publication describes also the following method in which the etch-back step of the method described above is omitted. First, silicon dioxide is buried into the same depth as the trench depth at the time of deposition by the bias ECR-CVD process. Next, the burying material layer made of silicon dioxide on the wide convex region is isotropically etched so that the shape of the burying material layer on the wide convex region is changed to the shape similar to the triangular shape on the convex regions having a small width. Thereafter, the triangular burying material layer is polished and planarized (see Example 2 and FIG. 3 of Japanese Unexamined Patent Publication No. HEI 5(1994)-275527).
Such means is applied to the formation of a flat inter-layer insulation film such as the formation of a trench capacitor involving burying of a groove, the formation of a trench contact (trench plug), the formation of a blanket W-CVD process, and so forth, besides the formation of trench isolation.
However, all the technologies described above are not yet free from the problem that the degree of polishing relies on an underlying pattern and planarization cannot be done sufficiently. This problem will be explained with reference to FIGS.
5
(
a
) to
5
(
c
) and FIGS.
6
(
d
) and
6
(
e
).
Three regions, that is, a wide convex region
9
, a region A having narrow convex patterns in a high density and a region B having narrow convex patterns in a low density, exist generally on a substrate
5
as shown in FIG.
5
(
a
). A lower layer
6
comprising a thin silicon oxide film as a polishing stopper layer and an upper layer
7
comprising a thin silicon nitride film exist on the upper surface of each convex portion. Burying material layers
23
and
24
are deposited to such a substrate
5
by deposition means that concurrently executes etching and deposition.
Next, a resist mask
8
having an opening at the portion thereof corresponding to the wide convex region
9
is formed, as shown in FIG.
5
(
b
).
The burying material layer
23
is isotropically etched at the end portion of the resist mask
8
until it reaches substantially the same size as that of the triangular shape of other regions. This etching provides triangular burying material layers
23
a
and
23
b
. Thereafter, the resist mask
8
is removed (see FIG.
5
(
c
)).
Polishing is then effected using a pad
10
. In this instance, polishing of the triangular convex portions can be made within a short time, and uniformity on a inner-surface of the wafer surface can be secured to a certain extent. However, the load varies depending on the number of convex portions because the density of the convex portions is different. In consequence, the polishing rate is low in the region A but is high in the region B and the wide convex region
9
as shown in FIG.
6
(
d
).
When the region A is polished, the wide convex region
9
is not recessed because the area of the polishing stopper layer is great, as shown in FIG.
6
(
e
). However, the region B is recessed with the result that polishing cannot be done uniformly.
Such a problem is likely to develop in the memory portion having a greater number of convex portions and in the peripheral circuit portion having a smaller number of convex portions.
The explanation given ab

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