Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1997-04-17
1999-01-12
Fourson, George R.
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438426, 438978, H01L 2176
Patent
active
058588574
ABSTRACT:
A method of forming shallow trenches in a semiconductor substrate is provided. This method allows the thus-formed trenches to be shaped with a rounded top corner having a desired radius of curvature in accordance with actual requirements. From experiments, it is learned that the radius of curvature of the top corners of the trenches decreases linearly with the depth of a pre-trench formed by over-etching in the substrate. The relationship between radius of curvature and depth of pre-trench can be pre-established by experimentation. After that, the top corners of the shallow trenches in the substrate can be controlled to be shaped with a desired radius of curvature by adjusting the depth of the pre-trench based on the pre-established linear relationship. In this method, the substrate is removed to a predetermined depth corresponding to the desired radius of curvature of the top corner of the to-be-formed trench; then, thermal oxidation is performed on the substrate so as to form an oxide layer on the exposed area of the substrate; and finally, the oxide layer is removed. The empty space left by the removed oxide layer serves as the desired trench.
REFERENCES:
patent: 4391409 (1983-07-01), Nakajima et al.
patent: 4407851 (1983-10-01), Kurosawa et al.
patent: 4471525 (1984-09-01), Sasaki
patent: 4622096 (1986-11-01), Dil et al.
patent: 4693781 (1987-09-01), Leung et al.
patent: 4892614 (1990-01-01), Chapman et al.
patent: 4916086 (1990-04-01), Takahashi et al.
patent: 4923821 (1990-05-01), Namose
patent: 5130268 (1992-07-01), Liou et al.
patent: 5350491 (1994-09-01), Fulford, Jr. et al.
patent: 5578518 (1996-11-01), Koike et al.
patent: 5728621 (1998-03-01), Zheng et al.
Wolf, S., "Silicon Processing for the VLSI Era:vol. 2, Process Integration", Lattice Press, pp. 54-55, 1990.
Fourson George R.
Winbond Electronics Corp.
LandOfFree
Method of forming top corner rounding of shallow trenches in sem does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming top corner rounding of shallow trenches in sem, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming top corner rounding of shallow trenches in sem will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1515089