Fishing – trapping – and vermin destroying
Patent
1991-08-14
1993-04-13
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437235, 437944, 148DIG100, H01L 2144
Patent
active
052022862
ABSTRACT:
A method of producing a three-dimensional feature on a substrate and adjacent electrically insulating films comprising producing a resist on a portion of a surface of a substrate; etching the substrate to remove portions of the substrate not covered by the resist, leaving an etched surface on part of the substrate, and producing a three-dimensional feature having side walls intersecting the etched surface of the substrate underlying and undercutting the resist so that the resist includes overhanging portions spaced from the etched surface of the substrate, the three-dimensional feature having a height between the resist and the etched surface of the substrate; depositing, in a chemical vapor deposition process at a relatively low temperature, a discontinuous electrically insulating film to a thickness no greater than the height of the three-dimensional feature in a first segment on the resist and in a second segment, discontinuous from the first segment, on the etched surface of the substrate adjacent the three-dimensional feature, including on the etched surface of the substrate between the etched surface of the substrate and the overhanging portions of the resist; and lifting off the resist and the first segment of the insulating film disposed on the resist to produce a flattened surface including the second segment of the insulating film and the three-dimensional feature.
REFERENCES:
patent: 4253888 (1981-03-01), Kikuchi
patent: 4268951 (1981-05-01), Elliott et al.
patent: 4503600 (1985-03-01), Nii et al.
patent: 4599137 (1986-07-01), Akiya
patent: 4601097 (1986-07-01), Shimbo
patent: 4685195 (1987-08-01), Szydlo et al.
patent: 4824800 (1989-04-01), Takano
patent: 4859618 (1981-08-01), Shikata et al.
patent: 5068207 (1991-11-01), Manocha et al.
Ghandhi, "VLSI Fabrication Principles", 1983, pp. 487-490 and p. 570.
Ehara et al, "Planar Interconnection Technology For LSI Fabrication Utilizing Lift-Off Process", Journal of the Electrochemical Society, vol. 131, No. 2, 1984, pp. 419-424.
Eng. abstract of Tano JP 63-138727.
Eng. abstract of Kurosawa et al. JP 58-53842.
Eng. abstract of FR 2,431,768.
S. Wolf, Silicon Processing for the VLSI Era, vol. 2, Lattice Press, Sunset Beach, 1990, pp. 237-238.
Hearn Brian E.
Holtzman Laura M.
Mitsubishi Denki & Kabushiki Kaisha
LandOfFree
Method of forming three-dimensional features on substrates with does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming three-dimensional features on substrates with , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming three-dimensional features on substrates with will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1155238