Method of forming thin film pseudo-planar FET devices and struct

Details Method of forming thin film pseudo-planar FET devices and struct Method of forming thin film pseudo-planar FET devices and struct

1993-03-22

1994-06-14

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 52, 437 59, 257 69, 257903, H01L 2170, H01L 2700

Patent

active

053209753

ABSTRACT:
A method of forming thin film pseudo-planar polysilicon gate PFETs (pPFETs) simultaneously with bulk PFET and NFET devices in a CMOS or BiCMOS semiconductor structure, comprising the steps of: providing a P-type silicon substrate having a surface that includes a plurality of isolation regions; delineating polysilicon lands at selected isolation regions; forming N-well regions into the substrate at a location where bulk PFETs are to be subsequently formed; forming insulator encapsulated conductive polysilicon studs to provide gate electrodes at desired locations of the structure; forming self-aligned source/drain regions of the bulk NFETs into the substrate; forming self-aligned source/drain regions of the bulk PFETs and pPFETs into the substrate and into the polysilicon lands, respectively; and forming contact regions to the selected locations that include the source/drain regions. In particular, the method finds application in the formation of polysilicon PFETs which are extensively used as load devices in six device (6D) SRAM cells.

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IEEE Journal of Solid-State Circuits, vol. 24, No. 6, Dec. 1989, pp. 1708-1713, Ando et al., "A 0.1-.mu. Standby Current, Ground-Bounce-Immune 1-Mbit CMOS SRAM".
The Jun. 1990 Symposium on VLSI Technology, 4.3, pp. 23-24, M. Kinugawa, et al. "TFT (Thin Film Transistor) Cell Technology for 4Mbit and More High Density SRAMs" 1990.
Solid State Technology, Jan. 1991, pp. 53-56, Nagy et al., "Planarized Inorganic Interlevel Dielectric for Multilevel Metallization--Part I".

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