Method of forming tapered plug-filled via in electrical intercon

Details Method of forming tapered plug-filled via in electrical intercon Method of forming tapered plug-filled via in electrical intercon

1994-12-15

1996-10-22

Fourson, George

Fishing, trapping, and vermin destroying

437192, 437194, 437947, 437981, H01L 2128

Patent

active

055676502

ABSTRACT:
A process for contouring a via formed in a dielectrics whereby a layer of a refractory metal is formed on the dielectric and in the via. The refractory metal layer is removed until a surface of the refractory metal within the via is below the upper surface of the dielectric. An etching process removes a portion of the dielectric and a tapered shape is formed at the intersection of the via and the upper surface of the dielectric. A second layer of metal is formed over the dielectric, with the second layer of metal extending into the vias and contacting the refractory metal with the tapered shape providing improved step coverage of the second layer of metal at the via.

REFERENCES:
patent: 5231051 (1993-07-01), Baldi et al.
patent: 5269880 (1993-12-01), Jolly et al.
patent: 5284799 (1994-02-01), Sato
patent: 5320979 (1994-06-01), Hashimoto et al.
patent: 5320981 (1994-06-01), Blalock
"Silicon Processing for the VLSI Era, vol. 2", S. Wolf, Lattice Press 1990, p. 191.
S. Wolf, "Silicon Processing for the VLSI Era, vol. 1", Lattice Press 1986, pp. 569-573.

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