Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2001-02-08
2002-07-09
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S700000, C438S734000, C438S778000
Reexamination Certificate
active
06417072
ABSTRACT:
FIELD OF INVENTION
The present invention relates to the manufacture of semiconductor integrated circuits and more particularly to a method of forming the STI oxide regions and alignment marks in a semiconductor structure provided with polysilicon filled deep trenches with only one masking step. STI (Shallow Trench Isolation) oxide regions are used to isolate devices from each other in the substrate and alignments marks are used in photolithography steps for reticle registration. The method finds extensive application in the field of DRAM (Dynamic Random Access Memory) and EDRAM (Embedded DRAM) chips where polysilicon filled deep and shallow trenches are formed in the semiconductor substrate.
BACKGROUND OF THE INVENTION
In the manufacture of semiconductor integrated circuits and especially in DRAM/EDRAM chips having polysilicon filled deep and shallow trenches formed in a silicon substrate, a specific MUV photolithography mask is used to create the alignment marks in the silicon structure that are required for reticle registration during the subsequent photolithography steps. For instance, DRAM chips wherein the elementary storage cell is of the so-called “BEST” type are concerned by such a masking step. “BEST” cells are described in the IBM Journal of Research and Development, Vol. 39, No ½ January/March 1995, in an article entitled “The Evolution of IBM CMOS Technology by E. Adler et al, pp 167-185.
Basically, at the end of the Deep Trench (DT) module, capacitor deep trenches have been etched in the silicon substrate. Next, the so-called active areas (AAs) are formed using a first mask referred to as the AA mask. Active areas include the source/drain regions of all the Insulated Gate Field Effect Transistors (IGFETs). Then, shallow isolation trenches are formed and a layer of an oxide, referred to hereinbelow as the STI oxide, is deposited to conformally coat the wafer surface, in order to fill the shallow isolation trenches in excess. The STI oxide layer is then planarized, i.e. the oxide on top of the AAs is removed and the oxide in the shallow isolation trenches etched down to approximately the silicon substrate level to create the so-called STI oxide regions. The planarization step is generally performed by Chemical-Mechanical Planarization (CMP). At this stage of the fabrication process, the wafer surface is substantially planar. These steps which are carried out in the STI module aim to isolate AAs from each other by said STI oxide regions. Afterwards, well and surface implants are performed before the gate conductor (GC) stack is deposited. The delineation of the GC stack to define the IGFET gate conductors requires the deposition of a photoresist layer and a DUV mask. The implants require MUV masks to prevent some regions of the wafer from being implanted. In order to successfully register these masks (both MUV implant masks and DUV GC mask) with a good accuracy, it is necessary to create alignment marks at the wafer surface. To date, this is the role of an additional MUV mask, referred to as the KV mask, which is formed right after STI oxide region formation. The above conventional fabrication process to form the STI oxide regions and the alignment marks with two masking steps will be now described in more details in conjunction with FIGS.
1
and
2
A-
2
I.
Turning to
FIG. 1
, there is shown the top view and a cross section taken along line aa thereof of a state-of-the-art semiconductor structure
10
which is part of the wafer at the end of the DT module, i.e. after polysilicon filled deep trenches have been formed. Basically, structure
10
consists of a silicon substrate
11
with a 140 nm thick Si3N4 pad layer
12
formed thereupon (the underlying SiO2 pad layer is not taken into consideration for the sake of simplicity). The Si3N4 pad layer is deposited on blanket wafers before deep trench formation, it will be used later on as an etch stop layer for various etch and CMP steps. As apparent in
FIG. 1
, two types of deep trenches labeled
13
A and
13
B have been formed in silicon substrate
11
. Trenches
13
A are formed in the “array” areas where the elementary memory cells are fabricated. Each memory cell is comprised of an IGFET and its associated capacitor that is formed in a deep trench as standard. Trenches
13
B are formed in the “support” and in the “kerf” areas where one can find addressing circuits, drivers, . . . and measurement/alignment structures respectively. Some trenches
13
B in the “kerf” areas will be used later on in the fabrication process as alignment marks. Deep trenches
13
A and
13
B are filled with polysilicon material as standard. The bottom part of the polysilicon fill
14
′, referred to hereinbelow as POLY
2
(POLY
1
is not shown in FIG.
1
), is isolated from the substrate by a collar oxide layer
15
and the top part
14
″ is referred to hereinbelow as POLY
3
.
Now, the exposed polysilicon material of POLY
3
is etched below substrate
11
surface to create recesses
16
A and
16
B that are shown in FIG.
2
A. These recesses and this etch step will be referred to hereinbelow as RECESS
3
and RECESS
3
etch step respectively. Typically, the depth of RECESS
3
in the silicon substrate
11
is about 50 nm. Note that the polysilicon of POLY
3
is arsenic (As) doped so that the out diffusion of As atoms into the silicon substrate
11
will subsequently form a strap making an electrical connection between one electrode of the capacitor and the source/drain region of the IGFETs. The strap is “buried” to avoid an electrical short between the capacitor and the passing word lines (WLs) that are the gate conductors of the IGFETs. The passing word lines will be defined later on in the wafer processing by the so-called GC mask of the DUV type.
A first masking step is now necessary to define the active areas (AAs). Turning to
FIG. 2B
, a 135 nm thick layer
17
of an anti-reflective coating (ARC) material is blanket deposited onto structure
10
, followed by the deposition of a 625 nm thick layer
18
of a photoresist. Adequate materials are AR3 900 and M20G supplied by Shipley USA, Malborough, Mass., USA. The ARC material is not only used for its anti-reflective properties, but also as a planarizing medium. The photoresist layer
18
is baked, exposed, and developed as standard to leave a patterned layer, that will be referred to hereinbelow as the AA mask still bearing numeral
18
.
After the AA mask
18
has been formed, the process continues with an adequate three-step anisotropic dry etch process, to remove the ARC, Si3N4, monocrystalline silicon of substrate
11
, polysilicon of POLY
3
/POLY
2
and the collar oxide in sequence with three different chemistries at locations that are not protected by the AA mask
18
. This etch process is performed in the MxP chamber provided with an electrostatic chuck ESC S
3
and a Vespel ring of an AME 5000, a tool sold by Applied Materials Inc, Santa Clara, Calif., USA.
Adequate operating conditions for each etch step are:
1. ARC Etching
Cathode temp.
20° C.
Wall temp.
45° C.
Pressure
45 mTorr
RF power
700 W
Magnetic field
15 G
CF4 flow
100 sccm
He Backside press.
26 Torr
Duration
Etch End Point Detection (EPD)
2. Si3N4 Etching
Cathode temp.
20° C.
Wall temp.
45° C.
Pressure
80 mTorr
RF power
600 W
Magnetic field
15 G
CHF3 flow
60 sccm
O2 flow
10 sccm
He Backside press.
8 Torr
Duration
EPD
3. Monocrystalline Silicon/POLY
3
/Collar Oxide Etching
Cathode temp.
20° C.
Wall temp.
45° C.
Pressure
35 mTorr
RF power
450 W
Magnetic field
0 G
NF3 flow
8 sccm
Ar flow
100 sccm
He Backside press.
8 Torr
Duration
260 sec
This sequence of etching steps referred to hereinbelow as the AA/STI etch step is used to create the shallow isolation trenches and the active areas in the silicon substrate
11
. Shallow isolation trenches will be subsequently filled with the STI oxide to form STI oxide regions. At this stage of the fabrication process, the structure
10
is shown in FIG.
2
C. As app
Coronel Philippe
Lacombe Philippe
Maccagnan Renzo
Pyonin Adam
Townsend Tiffany L.
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