Method of forming stacked tungsten gate PFET devices and structu

Details Method of forming stacked tungsten gate PFET devices and structu Method of forming stacked tungsten gate PFET devices and structu

1991-07-16

1992-05-12

Quach, T. N.

Fishing, trapping, and vermin destroying

437 57, 437192, 437193, 437228, 437915, 148DIG164, H01L 21283, H01L 2190, H01L 21335

Patent

active

051127652

ABSTRACT:
A manufacturing method is provided for producing a stacked semiconductor structure including: depositing a first thick passivating layer onto the base structure; forming first stud openings in the first thick passivating layer exposing at least one active region and/or one of the polysilicon lines; depositing a first layer of a conductive material to fill the first stud openings and define first contact studs, the upper part of some of the first contact studs comprising the gate electrodes of PFET devices; planarizing the structure to make the top surface of the first contact studs coplanar with the surface of the first thick passivating layer; depositing a thick insulating layer to form the gate dielectric of PFET devices and patterning it to define contact openings to expose selected first contact studs at desired locations; depositing a layer of polysilicon; patterning the polysilicon layer to define polysilicon lands containing the first contact studs at the desired locations; selectively implanting to define the source and drain regions of the PFET devices and interconnection conductors; depositing a cap layer; depositing a second thick passivating layer forming second stud openings in the second thick passivating layer to expose desired portions of the polysilicon lands and/or portions of the first contact studs; depositing a second layer of conductive material to define second contact studs; and planarizing the structure to make the top surface of the second contact studs coplanar with the surface of the second thick passivating layer.

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European Search Report of EP 90480109.

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