Method of forming stacked self-aligned polysilicon PFET devices

Details Method of forming stacked self-aligned polysilicon PFET devices Method of forming stacked self-aligned polysilicon PFET devices

1991-07-12

1992-03-31

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 56, 437 57, 437200, 437915, 437245, 437913, 437 52, H01L 21265

Patent

active

051008173

ABSTRACT:
A stacked semiconductor structure including a base structure (18/19) is comprised of a semiconductor substrate having active regions (21) of devices (N1, . . . ) formed therein and/or a plurality of polysilicon lines (23-1, . . . ) formed thereupon; a first thick passivating layer (26/27) having a set of first metal contact studs (30-1, . . . ) therein contacting at least one of said active regions (21) and/or said polysilicon lines (23-1, . . . ), the surface of said first metal contact studs being coplanar with the surface of said first thick passivating layer; a plurality of first polysilicon lands (31-1, . . . ) formed on the said thick passivating layer, certain portions of said first polysilicon lands defining the source, drain and channel regions forming the body of a PFET device with at least one region (SP1) contacting one of said first metal contact studs; a thin insulating layer (33) forming the gate dielectric layer of said PFET device; a plurality of highly doped second polysilicon lands (35-1A, . . . ) formed over by said thin insulating layer (33); a certain portion of said second polysilicon lands (35-1A, . . . ) forming the gate electrode (GP1) of said PFET device (SP1) which is self-aligned with said source (SP1) and drain (DP1) regions; a second thick passivating layer (37/38) having a set of second metal contact studs (40-1, . . . ) therein contacting at least one of said first or second polysilicon lands (31-1, . . . ; 35-1, . . . ) and/or said first contact studs (30-1, . . . ); the surface of said second metal contact studs is coplanar with the surface of said second thick passivating layer; a first metal interconnection configuration having metal lands (41-1, . . . ) electrically contacting at least one of said second metal contact studs (40-1, . . . ); and, a final insulating film (42).

REFERENCES:
patent: 4498226 (1985-02-01), Inoue et al.
patent: 4795722 (1989-01-01), Welch et al.
patent: 4868137 (1989-09-01), Kubota
patent: 4902637 (1990-02-01), Kondou et al.
patent: 4987099 (1991-01-01), Flanner

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