Method of forming stacked conductive and/or resistive polysilico

Details Method of forming stacked conductive and/or resistive polysilico Method of forming stacked conductive and/or resistive polysilico

1991-07-12

1994-01-04

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437228, 437918, 437192, H01L 213205, H01L 2198

Patent

active

052759636

ABSTRACT:
A semiconductor structure including: a semiconductor substrate (18/19) having active regions (21) of devices (T1, . . . ) therein and/or polysilicon lines (23-1, . . .) formed
thereupon; a first thick passivating layer (26/27) formed above the substrate having a set of first metal contact studs (30-1, . . .) therein contacting at least one of the active regions (21) and/or the polysilicon lines (23-1, . . . ); the surface of the first contact studs is coplanar with the surface of the first passivating layer; a plurality of polysilicon lands (31-1, . . .) formed on the planar structure in contact with the first contact studs; the polysilicon lands are either highly resistive, highly conductive or a mix thereof; a second thick passivating layer (34/35) formed above the resulting structure having a set of second metal contact-studs (37-1 . . .) therein contacting at least one of the polysilicon lands and/or one of the first contact studs; the surface of the second contact studs is coplanar with the surface of the second thick passivating layer. a plurality of metal lands (38-1, . . . ) formed above the second thick passivating layer (34/35) in contact with the second contact studs; a final insulating film (39).
The structure of the present invention may be advantageously used in chips implementing four device SRAM cells with stacked polysilicon load resistors (4D/2R SRAM cells) in CMOS FET technology.
The present invention also relates to the method for fabricating the same.

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