Method of forming source and drain of a...

Details Method of forming source and drain of a... Method of forming source and drain of a...

2008-10-10

2011-12-27

Pert, Evan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

C257S192000, C257S369000, C257SE27098, C257SE21661

Reexamination Certificate

active

08084788

ABSTRACT:
A semiconductor fabrication method involving the use of eSiGe is disclosed. The eSiGe approach is useful for applying the desired stresses to the channel region of a field effect transistor, but also can introduce complications into the semiconductor fabrication process. Embodiments of the present invention disclose a two-step fabrication process in which a first layer of eSiGe is applied using a low hydrogen flow rate, and a second eSiGe layer is applied using a higher hydrogen flow rate. This method provides a way to balance the tradeoff of morphology, and fill consistency when using eSiGe. Embodiments of the present invention promote a pinned morphology, which reduces device sensitivity to epitaxial thickness, while also providing a more consistent fill volume, amongst various device widths, thereby providing a more consistent eSiGe semiconductor fabrication process.

REFERENCES:
patent: 7214598 (2007-05-01), Capewell et al.
patent: 2008/0079033 (2008-04-01), Waite et al.
patent: 2008/0166847 (2008-07-01), Utomo et al.

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