Fishing – trapping – and vermin destroying
Patent
1995-03-01
1996-01-16
Chaudhuri, Olik
Fishing, trapping, and vermin destroying
437 31, 437 59, 437 63, 437 67, 148DIG10, 148DIG11, 148DIG12, 148DIG50, 148DIG151, 257347, 257507, H01L 21265
Patent
active
054847389
ABSTRACT:
A bonded, SOI wafer which has stepped isolation trenches and sublayer interconnections first formed in a bulk silicon wafer. After these process steps are complete, a thin polysilicon layer is formed on the planarized upper surface of the bulk silicon wafer. This thin polysilicon layer is then bound to an oxide layer on the surface of a separate wafer to form a bonded silicon-on-oxide structure. The entire assembly is, in effect inverted, and what had been the lower surface of the bulk silicon wafer, is removed to the bottom of the deepest trench step. In this bonded SOI structure, regions between the trenches are deep and suitable for bipolar device fabrication, while the trench steps form shallow regions suitable for fabrication of CMOS devices.
REFERENCES:
patent: 3385729 (1968-05-01), Larchian
patent: 3913121 (1975-10-01), Youmans et al.
patent: 4561172 (1985-12-01), Slawinski et al.
patent: 4672410 (1987-06-01), Miura et al.
patent: 4897362 (1990-01-01), Delgado et al.
patent: 4908328 (1990-03-01), Hu et al.
patent: 5164218 (1992-11-01), Tsuruta et al.
patent: 5298450 (1994-03-01), Verret
patent: 5356827 (1994-10-01), Ohoka
C. Harendt et al.; "Silicon-on-Insulator Films Obtained by Etchback of Bonded Wafers"; Journal of the Electrochemical Society, vol. 136, No. 11, Nov. 1989; pp. 3547-3548.
W. P. Maszara et al.; "Bonding of Silicon Wafers for Silicon-on-Insulator"; Journal of Applied Physics, vol. 64, No. 9, 1 Nov. 1988; pp. 4943-4950.
A. M. Healy; "Integrated Semiconductor Device"; IBM Technical Disclosure Bulletin, vol. 8, No. 7, 7 Dec. 1965; pp. 1016-1017.
Chu Shao-Fu S.
Hsieh Chang-Ming
Hsu Louis L. C.
Kim Kyong-Min
Mei Shaw-Ning
Chaudhuri Olik
Huberfeld Harold
International Business Machines - Corporation
Pham Long
LandOfFree
Method of forming silicon on oxide semiconductor device structur does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming silicon on oxide semiconductor device structur, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming silicon on oxide semiconductor device structur will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-309073