Method of forming silicon chicklet pedestal

Metal working – Method of mechanical manufacture – Electrical device making

Reexamination Certificate

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Details

C029S830000, C029S840000, C174S260000

Reexamination Certificate

active

07987591

ABSTRACT:
A silicon chicklet pedestal for use in a wafer-level test probe of a wafer is provided and includes a main body, first and second opposing faces, and an array of vias formed through the main body to extend between the first and second faces, through which pairs of leads, respectively associated with each via at the first and second faces, are electrically connectable to one another.

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Deng Chun et al.; “A MEMS Based Interposer for Nano-Wafer Level Packaging Test”; IEEE Xplore; http://ieeexplore.ieee.org/xpl/absprintf.jsp?arnumber-1271555&page=FREE; Sep. 2, 2008.
L Criscuolo; “Using Silicon Contacts to Test and Burn-In Flash Memory, Microprocessors, and FPGAs”; IEEE Xplore; http://ieeexplore.ieee.org/xpls/absprintf.jsp?arnumber=670813; Sep. 2, 2008.

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