Method of forming silicides having different thicknesses

Details Method of forming silicides having different thicknesses Method of forming silicides having different thicknesses

1988-05-31

1989-10-31

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 41, 437192, 437913, 148DIG19, 148DIG147, 357 71, H01L 21283

Patent

active

048777552

ABSTRACT:
A MOS transistor (10) having a thicker silicide layer (50) over a gate (30) than a silicide layer (44) over source and drain regions (42) is disclosed. A process of the present invention forms a first silicide barrier (28) overlying the gate (30) when the gate is formed. Next, a first silicide formation process forms the first silicide layer (44) overlying source and drain regions (42). The silicide barrier layer (28) prevents silicide formation over the gate (30). The silicide barrier (28) is removed, and another silicide barrier (48) is formed over the first silicide layer (44). A second silicide formation process forms the second silicide layer (50) over the gate (30). The silicide barrier layer (48) prevents expansion of the first silicide layer (44).

REFERENCES:
patent: 4445266 (1984-05-01), Mai et al.
patent: 4587718 (1986-05-01), Haken et al.
patent: 4740484 (1988-04-01), Norstrom et al.
patent: 4755478 (1988-07-01), Abernathey et al.
patent: 4821085 (1989-04-01), Haken et al.
Wolf et al., Silicon Processing, vol. 1-Process Technology, Lattice Press, 1984, pp. 384-405.
Murarka, "Self-Aligned Silicides or Metals for Very Large Scale Integrated Circuit Applications," J. Vac. Sci. Technol. B., vol. 4, No. 6, Nov./Dec. 1986, pp. 1325-1331.

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