Semiconductor device manufacturing: process – Chemical etching
Reexamination Certificate
2008-01-08
2008-01-08
Norton, Nadine G. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
C438S706000
Reexamination Certificate
active
11177216
ABSTRACT:
A substrate comprising a first transistor element and a second transistor element is provided. A layer of a material is deposited over the first transistor element and the second transistor element. A portion of the layer of material is modified, which may be done, e.g., by irradiating the portion with ions or performing an isotropic etching process to reduce its thickness. An etching process adapted to remove the modified portion of the layer of material more quickly than an unmodified portion of the layer located over the second transistor element is performed.
REFERENCES:
patent: 4839311 (1989-06-01), Riley et al.
patent: 6187620 (2001-02-01), Fulford, Jr. et al.
patent: 6696334 (2004-02-01), Hellig et al.
patent: 2004/0188769 (2004-09-01), Tsuno
patent: 2005/0051866 (2005-03-01), Wang et al.
patent: 2005/0106890 (2005-05-01), Schroeder et al.
patent: 196 54 738 (1997-07-01), None
Buchholtz Wolfgang
Lenski Markus
Raab Michael
Wei Andy
Advanced Micro Devices , Inc.
Dahimene Mahmoud
Norton Nadine G.
Williams Morgan & Amerson P.C.
LandOfFree
Method of forming sidewall spacers does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming sidewall spacers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming sidewall spacers will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3936844