Semiconductor device manufacturing: process – Electron emitter manufacture
Reexamination Certificate
2000-10-17
2001-11-06
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Electron emitter manufacture
C313S309000
Reexamination Certificate
active
06312966
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a field emission display device, and more specifically, to a method of forming sharp tip for field emission display device.
BACKGROUND OF THE INVENTION
Flat panel displays are widely used in a variety of applications, including computer displays. The flat panel display includes liquid crystal, plasma displays and a field emission display. The recent researches and development of display devices have been directed for thinner display structures. Under the consideration, the field emission displays (FED) having field emission cathodes have been one of the candidates. The field emission display device is a flat display device with a tip for emitting electrons. They are highly expected to be applicable in the area of a display of television pictures such as public relations display units. The FED is a flat CRT (cathode ray tube) having a field emission cathode, and an anode electrode and phosphors disposed opposite the field emission cathode in a position corresponding to each pixel.
Field emission displays typically include a generally planar substrate having an array of electron emitters. In many cases, the emitters are conical projections integral to the substrate. In the FED, electrons emitted from the field emission cathode are accelerated by an electric field between the field emission cathode and anode electrode and impact upon the phosphors which will be excited to emit light and display an image. In a conventional color display, each localized portion of the cathodoluminescent layer forms a green, red or blue sub-pixel of the color display.
To produce these emissions, FEDs have generally used a multiplicity of x-y addressable cold cathode emitters. There are a variety of designs such as point emitters, in which requisite electric field can be achieved at lower voltage levels. Each FED emitter is typically a miniature electron gun of micron dimensions. When a sufficient voltage is applied between the emitter tip and an adjacent extraction gate, electrons quantum mechanically tunnel out of the emitter. Generally, the anode is a transparent electrically conductive layer such as indium tin oxide (ITO) applied to the inside surface of a faceplate, as in a CRT. The field emission cathode used in the field emission type flat CRT of this type utilizes the tunnel effect of the electrons in a strong electric field. The electron-emitting materials include a high melting-point metals such as Mo, Ni, W, etc., and Si, etc.
FEDs require no heat or energy when they are off. When they operate, nearly all of the emitted electron energy is dissipated on phosphor bombardment and the creation of emitted unfiltered visible light. FEDs have the further advantage of a highly nonlinear current-voltage field emission characteristic, which permits direct x-y addressability without the need of a transistor at each pixel. Also, each pixel can be operated by its own array of FED emitters activated in parallel to minimize electronic noise and provide redundancy, so that if one emitter fails the pixel still operates satisfactorily.
The U.S. Pat. No. 5,608,283 discloses a field emission cathode plate in which particles of graphite, amorphous carbon or silicon carbon are provided on high-resistance pillars formed on a conductive layer provided on a substrate or directly on the conductive layer via an adhesive layer.
Further, U.S. Pat. No. 6,095,882 to Wells, et al., entitled “Method for forming emitters for field emission displays”. The method includes forming a hard mask layer on a substrate used to form emitters. On the hard mask layer, a photoresist layer is deposited. Islands of photoresist are exposed by an exposing energy through holes in a mask layer. Following the soft-bake, the substrate is flood exposed, and then developed, leaving behind hardened islands of exposed and baked photoresist. The hard mask layer is etched using the hardened islands as an etching barrier, and the substrate etched using the etched hard mask layer as an etching barrier. The etching continues until the substrate material below the etched hard mask layer is formed into an array of points of substrate. Once these emitter sites are formed, a field emission display having uniform emitters can be created.
In U.S. Pat. No. 6,116,975, the inventor disclosed a method of forming the field emission cathode. Sandhu, et al., disclosed a method of forming field emission device in U.S. Pat. No. 6,086,442, entitled” Method of forming field emission devices”. Also, the field emission cathode plate disclosed in the United States Patent is characterized in that the conductive particles are bonded to the conductive layer with a conductive adhesive. However, there is a large likelihood that the conductive adhesive material is likely to cover the conductive particles. In this case, electrons will not be emitted. It is difficult to dispose conductive particles selectively on the high-resistance pillars by the ordinary layer forming and printing techniques. U.S. Pat. No. 6,064,145 discloses a method of forming the tips for emitting. However, it includes a critical step to polish a dielectric layer and stop over the tip about 100 angstroms. As know in the technique, it is unlikely to control the CMP (chemical mechanical polishing) within such degree due to the 100 ANG may be the tolerance of the CMP. Therefore, this control is extremely difficult.
SUMMARY OF THE INVENTION
An object of the present invention is to manufacture tip of the field emission display device.
The present invention comprises providing a substrate having a trench. A first conductive layer is formed over the substrate to have a gap over the trench. A first dielectric layer is then formed on the first conductive layer. A portion of the first dielectric layer is removed to leave a residual dielectric layer in the gap. Next, isotropical etching is performed to etch the first conductive layer using the residual dielectric as an etching mask, thereby forming a conductive tip. A polishing stopper is formed over the conductive tip. A second dielectric layer is formed over the conductive tip and on the polishing stopper. The second dielectric layer is polished to the surface of the polishing stopper for preventing the conductive tip from being damage. A portion of the second dielectric layer is etched to form a step over the conductive tip. A second conductive layer is formed over the etched second dielectric layer. A portion of the second conductive layer is removed to expose an upper surface of the step. The second dielectric layer is etched using the second conductive layer as an etching mask. The polishing stopper is removed to expose the conductive tip.
REFERENCES:
patent: 6064145 (2000-05-01), Lee
patent: 6181060 (2001-01-01), Rolfson
Blakely , Sokoloff, Taylor & Zafman LLP
Hoang Quoc
Nelms David
Vanguard International Semiconductor Corporation
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