Method of forming shallow trench isolation structure

Details Method of forming shallow trench isolation structure Method of forming shallow trench isolation structure

1999-09-14

2001-07-17

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S700000

Reexamination Certificate

active

06261921

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application Ser. No. 88113097, filed Jul. 31, 1999, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to fabrication of a semiconductor device. More particularly, the present invention relates to a method of forming a shallow trench isolation structure (STI).
2. Description of Related Art
As semiconductor device integration continuously increases, device dimensions are necessarily accordingly reduced. An integrated circuit (IC) is composed of many devices and isolation structures that isolate the devices. The isolation structures, such as shallow trench isolation structures or field oxide isolation structures, are used to prevent carriers from moving between devices. Conventionally, the isolation structures are formed within a concentrated semiconductor circuit, for example, between adjacent field effect transistors (FET) in a dynamic random access memory (DRAM), to reduce a leakage current produced by the FET.
An isolation region is formed in an integrated circuit for preventing a short circuit from occurring between adjacent device regions on a substrate. Conventionally, a local oxidation of silicon (LOCOS) technique is widely utilized in the semiconductor industry to provide isolation regions on the semiconductor device. However, since internal stress is generated and bird's beak encroachment occurs in the isolation structures, LOCOS cannot effectively isolate devices.
The shallow trench isolation technique has been developed to improve the bird's beak encroachment of LOCOS so as to achieve an effective isolation structure. The conventional STI process is the sequential formation of a pad oxide layer and a silicon nitride layer on a substrate. A photolithography step is then performed to define STI areas. The silicon nitride layer, the pad oxide layer and the substrate are sequentially etched to form trenches in the substrate. Regions surrounded by STI are active areas (AA).
A liner oxide layer is formed on the surface of the trenches by thermal oxidation. A silicon dioxide layer is deposited in the trenches and above the silicon nitride mask layer by chemical vapor deposition (CVD). A chemical mechanical polishing (CMP) process is performed to remove the silicon dioxide layer that is higher than the silicon nitride layer to form a STI structure. Finally, hot phosphoric acid is used to remove the silicon nitride layer, and HF solution is used to remove the pad oxide layer.
Since the shallow trench isolation structure has a good isolation effect and its size is scaleable, it is often employed as a device isolation structure. The shallow trench isolation structure is the preferred isolation technique, especially for the fabrication of sub-half micron semiconductor devices.
FIG. 1
is a cross-sectional view schematically illustrating a conventional shallow trench isolation structure. As shown in
FIG. 1
, because the liner silicon dioxide layer
110
and the shallow trench isolation structure
120
are both made of silicon dioxide, a portion of the liner silicon dioxide layer
110
and a portion of the shallow trench isolation structure
120
are etched during the pad oxide layer etching process. A divot
130
is easily formed near the top corner of the shallow trench isolation structure
120
due to stress at the top corner of the shallow trench isolation structure
120
. A depth of the divot
130
is about 800-1000 Å. The divot
130
leads to a kink effect that causes a threshold voltage reduction. Moreover, in the subsequent poly gate process, polysilicon may fills the divot
130
, so that a leakage current is generated. Therefore, the process window of the subsequent poly gate process should be narrowed to avoid the leakage current.
A pullback process is used to avoid the formation of the divot in the shallow trench isolation structure. The pullback process is described as follows. A portion of the silicon nitride layer is etched by, for example, wet etching with hot phosphoric acid to widen the opening in the silicon nitride layer. Therefore, the subsequently formed silicon dioxide layer not only fills the trench but also covers the pad oxide layer. When the pad oxide layer is removed with HF solution, no divot is formed in the shallow trench isolation structure even a portion of the shallow trench isolation structure is etched. In this manner, the leakage current is avoided.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a method of forming a shallow trench isolation structure to avoid the formation of the divot. In this invention, the top corner of the shallow trench isolation structure is round to reduce stress at the top corner, so that the formation of the divot is avoided.
The present invention provides a method of forming a shallow trench isolation structure. A mask layer and a photoresist layer with an opening are formed on a substrate in sequence. The photoresist layer serves as an etching mask, and then a portion of the mask layer and a portion of the substrate are etched to form a trench in the substrate. A portion of the photoresist layer is removed by isotropic etching process, and the opening is widened. Then, a portion of the mask layer exposed by the widened opening is removed. In addition, a top corner of the trench is round after removing the portion of the mask layer. Finally, the trench is filled with an insulation material to form a shallow trench isolation structure.
Preferably, the portion of the photoresist layer mentioned above is removed by chemical downstream etching, and the removed thickness is about 180-220 Å. The etching gases that can be used here are CF
4
, O
2
and N
2
, and the flow rate is about 150 to about 250 sccm, about 150 to about 250 sccm and about 20 to about 40 sccm, respectively. The pressure is about 40 to about 50 Pa, and the RF power is about 500 to about 700 watts. As the mask layer is made of silicon nitride, the portion of the mask layer is removed by reactive ion etching. The reactive ion etching process necessarily has a high mask layer to substrate etching selectivity. In accordance with the etching selectivity, the etching gases that can be used here are CH
3
F and O
2
, and the flow rate is about 12 to about 16 sccm and about 36 to about 44 sccm, respectively. The pressure is about 45 to about 55 mtorr, and the RF power is about 200 to about 250 watts.
The feature of this invention is that the opening in the photoresist layer is widened by an etching step performed at a low etching rate. Then, the photoresist layer serves as a mask while removing a portion of the mask layer. Moreover, the rounded corner is formed at the top corner of the trench after the process of removing the portion of the mask layer; thus, stress at the top corner is reduced, and divot formation is avoided. Furthermore, the process window of the poly gate process is widened.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5989975 (1999-11-01), Kuo
patent: 5994229 (1999-11-01), Chen et al.
patent: 6001706 (1999-12-01), Tan et al.
patent: 6025249 (2000-02-01), Kuo
patent: 6121110 (2000-09-01), Hong et al.
patent: 6140206 (2000-10-01), Li et al.
patent: 6140242 (2000-10-01), Oh et al.
patent: 6174786 (2001-01-01), Kelley et al.

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