Method of forming shallow trench isolation structure

Details Method of forming shallow trench isolation structure Method of forming shallow trench isolation structure

2000-07-28

2001-08-21

Pham, Long (Department: 2823)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S435000, C438S437000

Reexamination Certificate

active

06277709

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing an isolation of integrated circuits. More particularly, the present invention relates to a method for manufacturing a shallow trench isolation.
2. Description of the Related Art
A complete integrated circuit is composed of a plurality of metal oxide semiconductor (MOS) transistors. Device isolation structures are used for isolating neighboring semiconductor devices so that any short circuiting between them is prevented. The conventional method of isolating semiconductor devices includes forming a field oxide (FOX) layer on a substrate by local oxidation of silicon (LOCOS). However, the field oxide layer that is formed has several problems. Considerable stresses are created at the junction between the field oxide layer and the substrate. Moreover, bird's beak regions are created around the periphery of the isolation structure. Consequently, IC devices that use (FOX) isolation structures are less amenable to high-density packing.
Shallow trench isolation is another method for isolating semiconductor devices. Shallow trench isolation entails the following procedures. First an anisotropic etching operation is conducted to form a trench in the semiconductor substrate. The trench is subsequently filled with silicon oxide. Since shallow trench isolation can prevent bird's beak encroachment, associated with the LOCOS method, it is an ideal method for forming deep sub-micron devices.
FIGS. 1A through 1C
are schematic cross-sectional views showing the progression of steps for producing a conventional shallow trench isolation structure.
As shown in
FIG. 1
, a pad oxide layer
102
and a silicon nitride layer
104
are formed over the substrate
100
. Using the silicon nitride layer
104
as an etching mask, a trench
106
is etched in the substrate
100
. A linear oxide layer
108
is formed on the surface of the exposed portion of the substrate
100
. A silicon oxide layer
110
is formed above the substrate
100
, covering the silicon nitride layer
104
and filling the trench
106
.
As shown in
FIG. 1B
, the silicon nitride layer
104
is used as a polishing stop layer to carry out a chemical mechanical polishing operation to remove excess silicon oxide layer and leave the silicon oxide layer
110
within the trench
106
.
As shown in
FIG. 1C
, the silicon nitride layer
104
is removed. Through the application of hydrofluoric acid the pad oxide layer
102
is subsequently removed, leaving the isolation region formed by the silicon oxide layer
100
in the trench
106
.
The size of devices and shallow trench isolation structures must be reduced, in order to enable higher levels of integration among high-density integrated circuits. In order to assure the effective isolation of devices, a predetermined width for shallow trench isolation structures must be established. Raising the concentration leads to a reduction in the surface area of the trench. A reduction in surface area of the trench increases the aspect ratio of the trench and, as a consequence, makes filling the trench more difficult. Specifically, if isolation material is not applied properly, then voids will formed within the shallow trench isolation structure.
SUMMARY OF THE INVENTION
Accordingly, one objective of this invention is to provide a method of manufacturing a shallow trench isolation structure that lowers the aspect ratio of a trench, facilitate the filling of the trench with isolation material, and thus enhance the effectiveness of the isolation structure.
As embodied and broadly described herein, the invention provides a method of manufacturing a shallow trench isolation structure. A pad oxide layer and a mask layer are sequentially formed over a substrate. Through a lithographic and etching procedure, portions of the mask layer, the pad oxide layer, and the substrate are removed forming a trench. The oxidation step is performed to cause the substrate within the trench to form a linear oxide layer. The linear oxide layer on the bottom of the trench is removed to expose the bottom of the trench. A polysilicon layer, deposited over the surface of the wafer, covers the mask layer and fills the trench. An etching procedure is used to remove the polysilicon layer higher than the mask layer. The remaining portion of the polysilicon layer within the trench forms a polysilicon plug. A thin, conformal barrier layer is subsequently deposited over the substrate. An isolation layer is then deposited over the barrier layer. A chemical mechanical polishing procedure is then conducted to remove insulating material as well as the barrier layer on top of the mask layer and outside the trench. The mask layer is removed.
The method of manufacturing shallow trench isolation structures provided in this invention lowers the aspect ratio of the trench used to fill the isolation layer. Consequently, difficulties associated with filling the trench are reduced.
Oxidation of polysilicon used to fill the trench may occur in subsequent stages of the process. The silicon dioxide, formed as a result of oxidation, possesses greater volume. This change in volume produces a great deal of stress on the device and affects its performance. Thus, the method of this invention provides a barrier layer covering the polysilicon layer. Thereafter, a isolation layer is formed thereon. In this way, further oxidation of the polysilicon layer can be avoided.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5099304 (1992-03-01), Takemura et al.
patent: 5316978 (1994-05-01), Boyd et al.
patent: 5994200 (1999-11-01), Kim

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