Method of forming shallow trench isolation for thin...

Details Method of forming shallow trench isolation for thin... Method of forming shallow trench isolation for thin...

2001-06-29

2003-07-29

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S155000, C438S259000, C438S588000, C438S692000

Reexamination Certificate

active

06599813

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the manufacture of semiconductor devices, and more particularly to a method of forming shallow trench isolation (STI) for semiconductor integrated circuits on thin silicon-on-insulator (SOI) substrates.
BACKGROUND OF THE INVENTION
In the formation of semiconductor integrated circuits, it is necessary to isolate discrete semiconductor devices such as field effect transistors (FETs) using various field oxide isolations. In advanced semiconductor integrated circuit schemes, shallow trenches are often used in a silicon substrate, to minimize the field oxide feature size. Such trenches are filled with silicon dioxide (SiO
2
), typically by chemical vapor deposition (CVD). Excess SiO
2
is then removed either by etching or chemical mechanical polishing (CMP) to form the field oxide isolation, which is commonly referred to as shallow trench isolation (STI).
However, there are several problems associated with applying current STI formation processes to silicon-on-insulator (SOI) substrates, requiring STI oxide fill of very shallow depths below 1000 Å. For example, relatively large variations in STI oxide thickness can occur due to erosion of the STI oxide during oxide etches in current STI formation processes, such as pad oxide and sacrificial oxide stripping steps, as explained below.
A typical STI formation process begins with formation of a pad oxide layer on top of the silicon substrate, followed by deposition of a polish stop layer such as silicon nitride. Next, a trench is formed in the polish stop layer, pad oxide layer and silicon substrate, using conventional photolithography masking and etching techniques. A sidewall oxide may be thermally grown on the silicon sidewalls of the trench, to reduce the field emission effect. Then, the trench is filled with SiO
2
by, for example, a high density plasma (HDP) deposition process. Excess SiO
2
is removed by CMP planarization down to the polish stop layer, and the polish stop layer is then removed.
Next, well ion implants are performed. Before implant, the previously grown pad oxide layer is removed by etching. During etching, some of the STI oxide fill is also inevitably removed. Next, a sacrificial oxide layer is grown on the silicon substrate. Then, well ion implants are performed. Ion implant of the SiO
2
STI fill is believed to cause the surface of the SiO
2
to become very soft. Upon stripping of the sacrificial oxide layer, a significant amount of the softened SiO
2
STI fill material is also removed. Removal of SiO
2
STI fill material during removal of pad oxide and sacrificial oxide layers not only causes relatively large variations in STI oxide thickness, but also creates divots between the STI and the silicon substrate.
Following well ion implant, the polysilicon gate is formed as follows. First, a layer of polysilicon is deposited over the substrate surface. Then, a gate is defined in the polysilicon layer by conventional photolithography masking and etching techniques. However, polysilicon rails often remain on the sidewalls of the divots created between the STI and the silicon substrate. These rails may cause electrical shorts between gates, thereby affecting integrated circuit yield and reliability.
These problems are of increasing concern as integrated circuit feature size becomes smaller and device density becomes larger. In addition, these problems are of particular concern with regard to STI formed by conventional processes on SOI substrates. SOI substrates are comprised of a thin silicon layer on top of a buried oxide layer. The thin silicon layer typically has a thickness of less than 1000 Å, and more usually about 500 Å. The buried oxide layer typically has a thickness of about 1000 Å to 1500 Å. STI thickness control and divot elimination have not been achievable using convention STI formation processes with SOI substrates.
SUMMARY OF THE INVENTION
The aforementioned problems are addressed by the method of the present invention. In accordance with the present invention, a method is disclosed for forming shallow trench isolation (STI) on a silicon-on-insulator (SOI) substrate, wherein said SOI substrate comprises a silicon layer on top of a buried oxide layer. The method comprises the steps of: forming a gate oxide layer on said silicon layer; depositing a first polysilicon layer on said gate oxide layer; depositing a polish stop layer on said first polysilicon layer; forming a plurality of trenches in said substrate, wherein said trenches have a depth extending through said polish stop layer, said first polysilicon layer, said gate oxide layer, and said silicon layer; conformally depositing a silicon oxide layer in said trenches and on said polish stop layer; removing a first portion of said silicon oxide layer by chemical mechanical polishing, such that the top surface of said silicon oxide layer in said trenches is polished down to the same height as the top surface of said polish stop layer; removing a second portion of said silicon oxide layer by etching, such that the top surface of said silicon oxide layer is etched down to a height below the top surface of said polish stop layer and above the top surface of said first polysilicon layer; removing said polish stop layer; depositing a second polysilicon layer on said silicon oxide layer and said first polysilicon layer; and forming a polysilicon gate comprised of said first and second polysilicon layers by photolithography masking and anisotropic etching said first and second polysilicon layers.


REFERENCES:
patent: 4692992 (1987-09-01), Hsu
patent: 4806501 (1989-02-01), Baldi et al.
patent: 4881105 (1989-11-01), Davari et al.
patent: 5177028 (1993-01-01), Manning
patent: 5466617 (1995-11-01), Shannon
patent: 5534450 (1996-07-01), Kim
patent: 5731241 (1998-03-01), Jang et al.
patent: 5770484 (1998-06-01), Kleinhenz
patent: 5837612 (1998-11-01), Ajuria et al.
patent: 5851900 (1998-12-01), Chu et al.
patent: 5854120 (1998-12-01), Urano et al.
patent: 5874328 (1999-02-01), Liu et al.
patent: 5882969 (1999-03-01), Krautschneider et al.
patent: 5937286 (1999-08-01), Abiko
patent: 5956583 (1999-09-01), Fuller
patent: 5963818 (1999-10-01), Kao et al.
patent: 5994178 (1999-11-01), Wu
patent: 5998261 (1999-12-01), Hofmann et al.
patent: 6001706 (1999-12-01), Tan et al.
patent: 6008095 (1999-12-01), Gardner et al.
patent: 6060748 (2000-05-01), Uchida et al.
patent: 6073004 (2000-06-01), Balachandran
patent: 6074904 (2000-06-01), Spikes, Jr. et al.
patent: 6076028 (2000-06-01), Donnelly et al.
patent: 6087233 (2000-07-01), Roh
patent: 6110788 (2000-08-01), Violette et al.
patent: 6133610 (2000-10-01), Bolam et al.
patent: 6144086 (2000-11-01), Brown et al.
patent: 6146970 (2000-11-01), Witek et al.
patent: 6153918 (2000-11-01), Kawashima et al.
patent: 6281095 (2001-08-01), Bolam et al.
patent: 6323125 (2001-11-01), Soo et al.
patent: 6333232 (2001-12-01), Kunikiyo
patent: 6361415 (2002-03-01), Sethuraman et al.
patent: 6380599 (2002-04-01), Fazan et al.
patent: 406267985 (1994-09-01), None
patent: 86116978 (1986-11-01), None

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