Method of forming shallow trench isolation

Details Method of forming shallow trench isolation Method of forming shallow trench isolation

2001-10-09

2003-07-08

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S437000, C438S700000, C438S703000, C257S506000, C257S524000

Reexamination Certificate

active

06589854

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90115359, filed Jun. 26, 2001.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to an electrical insulation structure and its method of manufacture. More particularly, the present invention relates to a shallow trench isolation (STI) structure and its method of manufacture.
2. Description of Related Art
Following the rapid advance in semiconductor manufacturing technologies, the level of integration is increased. As the dimensions of each device are reduced, an electrical insulating structure such as a layer of silicon oxide formed by a local oxidation (LOCOS) is unsatisfactory. At present, the most widely adopted method for electrical isolation is shallow trench isolation (STI).
In general, the silicon oxide within an STI structure is deposited by a high-density plasma chemical vapor deposition (HDPCVD) method. The HDPCVD method is actually a process that provides two concurrent mechanisms, namely, etching and deposition. In other words, a portion of the drop-off material is simultaneously etched during deposition. Hence, the process is able to provide a high gap-filling capacity ideal for depositing silicon oxide into a shallow trench structure.
FIGS. 1A through 1D
are schematic cross-sectional views showing the progression of steps for forming a shallow trench isolation (STI) structure according to a conventional method. As shown in
FIG. 1A
, a substrate is provided. A pad oxide layer
102
and a silicon nitride mask layer
104
are sequentially formed over the substrate
100
. An anisotropic etching is conducted to remove a portion of the silicon nitride mask layer
104
, the pad oxide layer
102
and the substrate
100
to form a trench
106
. After the anisotropic etching, a rounded corner structure
108
is also formed near the top of the trench
106
. The reason for forming the rounded corners
108
is because a sharp corner often leads to an insufficient thickness of subsequently formed gate oxide layer resulting in a leakage current. A rounded structure
108
can prevent such leakage due to an uneven gate layer thickness.
As shown in
FIG. 1B
, a high-density plasma chemical vapor deposition (HDPCVD) process is conducted. A silicon oxide layer
110
is formed over the entire substrate
100
completely filling the trench
106
. Although HDPCVD provides high gap-filling capacity for silicon oxide, deposition on the trench wall near the rounded structure
108
often leads to the formation of blobs of silicon oxide that prevents the filling of oxide material underneath. Consequently, a weak spot
112
is created around that region.
As shown in
FIG. 1C
, chemical-mechanical polishing (CMP) of the silicon oxide layer
110
is conducted to remove a portion of the silicon oxide material outside the trench
106
. The silicon nitride mask layer
104
serves as a polishing stop layer.
As shown
FIG. 1D
, a wet etching process is conducted to remove the silicon nitride mask layer
104
and the pad oxide layer
102
sequentially, ultimately forming an STI structure
114
.
However, because the weak spots
112
are a region without silicon oxide filling, recess cavities
116
are formed at the upper corner of the trench
106
next to the substrate
100
in the final STI structure
114
. Such recess cavities
116
at the corner region of an STI structure not only expose the substrate
100
, but also render the exposed section of the substrate
100
vulnerable to damages in subsequent processing.
In the aforementioned process, the recess cavities
116
at the upper corners of the trench structure expose a portion of the substrate
100
and the exposed portion is vulnerable to processing damages. In addition, the recess cavity areas
116
are often centers for charge accumulation, leading to possible leakage current and a lowering of the threshold voltage of a gate oxide layer.
To reduce the formation of weak spots, a high-density plasma chemical vapor deposition (HDPCVD) process having a high etching/deposition ratio is often used to deposit insulating material into the trench of an STI structure. Because a higher etching/deposition ratio increases gap-filling capacity of a HDPCVD process and also induces a “re-deposition” effect, thus no weak spots are formed during insulating material deposition. However, a HDPCVD with a high etching/deposition has a lower deposition rate and hence is likely to decrease overall throughput of production.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a method of forming a shallow trench isolation (STI) structure capable of preventing the formation of weak spots after insulating material deposition.
A second object of this invention is to provide a method of forming a shallow trench isolation (STI) structure capable of preventing the formation of recess cavities that expose the substrate at the corner regions of the STI structure. Thus, damages to the substrate during subsequent processing are minimized.
A third object of this invention is to provide a method of forming a shallow trench isolation (STI) structure capable of preventing the formation of a recess cavity at the corner of the STI structure so that current leakage from the cavity region is avoided.
A fourth object of this invention is to provide a method of forming a shallow trench isolation (STI) structure capable of providing a balance between the number of weak spots created within the STI structure and the throughput of production so that an optimal production efficiency is obtained.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of forming an STI structure. First, a substrate is provided. A pad oxide layer is formed over the substrate. A mask layer is formed over the pad oxide layer. The substrate is patterned to form a trench in the substrate. A high-density plasma chemical vapor deposition (HDPCVD) is conducted to form an insulation layer over the substrate that also completely fills the trench. The HDPCVD is conducted in two separate stages. In the first stage, a HDPCVD process with a higher etching/deposition ratio is used so that the formation of weak spots inside the insulating material is prevented. In the second stage, a HDPCVD process with a lower etching/deposition ratio is used so that a higher depositing rate than the depositing rate in the first stage results. Hence, the overall throughput in the two-stage HDPCVD deposition is increased over a one-stage HDPCVD deposition employing a high etching/deposition ratio, and at the same time without creating too many internal weak spots. Thereafter, insulating material outside the trench region is removed. Finally, the mask layer and the pad oxide layer are sequentially removed to form a complete STI structure.
One major aspect of this invention is the use of a two-stage high-density plasma chemical vapor deposition to form an insulation layer over the substrate. Since a higher etching/deposition ratio increases gap-filling capacity and induces a “re-deposition” effect, no weak spots are formed in the first stage HDPCVD process.
Once the first stage HDPCVD process resolves the weak spot issue, a second stage HDPCVD process using a lower etching/deposition ratio can be employed. Since the deposition rate is higher for a HDPCVD process at a lower etching/deposition ratio, overall throughput is increased leading to higher production efficiency.
In addition, all two HDPCVD processing stages can be carried out inside the same reaction chamber. Since no additional equipment or step is required, no other cost or additional processing complexity is incurred.
Since the insulation layer is free of any weak spots, a recess cavity that exposes a portion of the substrate is absent from the STI structure. Hence, damages to the exposed substrate near the recess cavity are prevented.
Furthermore, the absence of recess cavities around the STI

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